xref: /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/gpio/mtgpio.c (revision a92b02566e23ca73f9874555335dc6b19f0f242c) 
1*aebd4dc8Smtk20895 /*
2*aebd4dc8Smtk20895  * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3*aebd4dc8Smtk20895  *
4*aebd4dc8Smtk20895  * SPDX-License-Identifier: BSD-3-Clause
5*aebd4dc8Smtk20895  */
6*aebd4dc8Smtk20895 
7*aebd4dc8Smtk20895 #include <assert.h>
8*aebd4dc8Smtk20895 #include <mtgpio.h>
9*aebd4dc8Smtk20895 #include <platform_def.h>
10*aebd4dc8Smtk20895 
mt_gpio_find_reg_addr(uint32_t pin)11*aebd4dc8Smtk20895 uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
12*aebd4dc8Smtk20895 {
13*aebd4dc8Smtk20895 	uintptr_t reg_addr = 0U;
14*aebd4dc8Smtk20895 	struct mt_pin_info gpio_info;
15*aebd4dc8Smtk20895 
16*aebd4dc8Smtk20895 	assert(pin < MAX_GPIO_PIN);
17*aebd4dc8Smtk20895 
18*aebd4dc8Smtk20895 	gpio_info = mt_pin_infos[pin];
19*aebd4dc8Smtk20895 
20*aebd4dc8Smtk20895 	switch (gpio_info.base & 0x0f) {
21*aebd4dc8Smtk20895 	case 0:
22*aebd4dc8Smtk20895 		reg_addr = IOCFG_BM_BASE;
23*aebd4dc8Smtk20895 		break;
24*aebd4dc8Smtk20895 	case 1:
25*aebd4dc8Smtk20895 		reg_addr = IOCFG_BL_BASE;
26*aebd4dc8Smtk20895 		break;
27*aebd4dc8Smtk20895 	case 2:
28*aebd4dc8Smtk20895 		reg_addr = IOCFG_BR_BASE;
29*aebd4dc8Smtk20895 		break;
30*aebd4dc8Smtk20895 	case 3:
31*aebd4dc8Smtk20895 		reg_addr = IOCFG_LM_BASE;
32*aebd4dc8Smtk20895 		break;
33*aebd4dc8Smtk20895 	case 4:
34*aebd4dc8Smtk20895 		reg_addr = IOCFG_RB_BASE;
35*aebd4dc8Smtk20895 		break;
36*aebd4dc8Smtk20895 	case 5:
37*aebd4dc8Smtk20895 		reg_addr = IOCFG_TL_BASE;
38*aebd4dc8Smtk20895 		break;
39*aebd4dc8Smtk20895 	default:
40*aebd4dc8Smtk20895 		break;
41*aebd4dc8Smtk20895 	}
42*aebd4dc8Smtk20895 
43*aebd4dc8Smtk20895 	return reg_addr;
44*aebd4dc8Smtk20895 }
45