1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <common/debug.h> 8 #include <lib/mmio.h> 9 #include <mtk_sip_svc.h> 10 #include <plat_dfd.h> 11 12 static bool dfd_enabled; 13 static uint64_t dfd_base_addr; 14 static uint64_t dfd_chain_length; 15 static uint64_t dfd_cache_dump; 16 17 static void dfd_setup(uint64_t base_addr, uint64_t chain_length, 18 uint64_t cache_dump) 19 { 20 mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL); 21 mmio_write_32(MTK_WDT_INTERVAL, MTK_WDT_INTERVAL_VAL); 22 mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL); 23 mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL); 24 25 /* Bit[2] = 0 (default=1), disable dfd apb bus protect_en */ 26 mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 0x1 << 2); 27 28 /* Bit[0] : enable?mcusys_vproc?external_off?dfd?trigger -> 1 */ 29 mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); 30 31 /* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */ 32 /* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */ 33 sync_writel(DFD_INTERNAL_CTL, 0x5); 34 35 /* bit[13]: xreset_b_update_disable */ 36 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); 37 38 /* 39 * bit[10:3]: DFD trigger selection mask 40 * bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger) 41 * bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger) 42 * bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger) 43 * bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger) 44 * bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger) 45 */ 46 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); 47 48 /* 49 * bit[9] : rg_rw_dfd_trigger_sel[6] = 1(cpu_eb_sw_dfd_trigger) 50 * bit[10] : rg_rw_dfd_trigger_sel[7] = 1(cpu_eb_wdt_dfd_trigger) 51 */ 52 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); 53 54 /* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */ 55 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); 56 57 /* 58 * bit[0]: rg_rw_dfd_auto_power_on = 1 59 * bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us) 60 * bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us) 61 */ 62 mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); 63 64 /* longest scan chain length */ 65 mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); 66 67 /* bit[1:0]: rg_rw_dfd_shift_clock_ratio */ 68 mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); 69 70 /* rg_dfd_test_so_over_64 */ 71 mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); 72 73 /* DFD3.0 */ 74 mmio_write_32(DFD_TEST_SI_0, 0x0); 75 mmio_write_32(DFD_TEST_SI_1, 0x0); 76 mmio_write_32(DFD_TEST_SI_2, 0x0); 77 mmio_write_32(DFD_TEST_SI_3, 0x0); 78 79 /* for iLDO feature */ 80 sync_writel(DFD_POWER_CTL, 0xF9); 81 82 /* read offset */ 83 sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL); 84 85 /* for DFD-3.0 setup */ 86 sync_writel(DFD_V30_CTL, 0xD); 87 88 /* set base address */ 89 mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); 90 mmio_write_32(DFD_O_REG_0, 0); 91 92 /* setup global variables for suspend and resume */ 93 dfd_enabled = true; 94 dfd_base_addr = base_addr; 95 dfd_chain_length = chain_length; 96 dfd_cache_dump = cache_dump; 97 98 if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { 99 mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL); 100 sync_writel(DFD_V35_ENABLE, 0x1); 101 sync_writel(DFD_V35_TAP_NUMBER, 0xB); 102 sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); 103 sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); 104 105 /* Cache dump only mode */ 106 sync_writel(DFD_V35_CTL, 0x1); 107 mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF); 108 mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL); 109 mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL); 110 mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL); 111 mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL); 112 113 if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) { 114 sync_writel(DFD_HW_TRIGGER_MASK, 0xC); 115 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); 116 } 117 } 118 dsbsy(); 119 } 120 121 void dfd_resume(void) 122 { 123 if (dfd_enabled == true) { 124 dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); 125 } 126 } 127 128 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, 129 uint64_t arg2, uint64_t arg3) 130 { 131 uint64_t ret = 0L; 132 133 switch (arg0) { 134 case PLAT_MTK_DFD_SETUP_MAGIC: 135 INFO("[%s] DFD setup call from kernel\n", __func__); 136 dfd_setup(arg1, arg2, arg3); 137 break; 138 case PLAT_MTK_DFD_READ_MAGIC: 139 /* only allow to access DFD register base + 0x200 */ 140 if (arg1 <= 0x200) { 141 ret = mmio_read_32(MISC1_CFG_BASE + arg1); 142 } 143 break; 144 case PLAT_MTK_DFD_WRITE_MAGIC: 145 /* only allow to access DFD register base + 0x200 */ 146 if (arg1 <= 0x200) { 147 sync_writel(MISC1_CFG_BASE + arg1, arg2); 148 } 149 break; 150 default: 151 ret = MTK_SIP_E_INVALID_PARAM; 152 break; 153 } 154 155 return ret; 156 } 157