1*3b994a75SRex-BC Chen /* 2*3b994a75SRex-BC Chen * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*3b994a75SRex-BC Chen * 4*3b994a75SRex-BC Chen * SPDX-License-Identifier: BSD-3-Clause 5*3b994a75SRex-BC Chen */ 6*3b994a75SRex-BC Chen #include <arch_helpers.h> 7*3b994a75SRex-BC Chen #include <common/debug.h> 8*3b994a75SRex-BC Chen #include <lib/mmio.h> 9*3b994a75SRex-BC Chen #include <mtk_sip_svc.h> 10*3b994a75SRex-BC Chen #include <plat_dfd.h> 11*3b994a75SRex-BC Chen 12*3b994a75SRex-BC Chen static bool dfd_enabled; 13*3b994a75SRex-BC Chen static uint64_t dfd_base_addr; 14*3b994a75SRex-BC Chen static uint64_t dfd_chain_length; 15*3b994a75SRex-BC Chen static uint64_t dfd_cache_dump; 16*3b994a75SRex-BC Chen 17*3b994a75SRex-BC Chen static void dfd_setup(uint64_t base_addr, uint64_t chain_length, 18*3b994a75SRex-BC Chen uint64_t cache_dump) 19*3b994a75SRex-BC Chen { 20*3b994a75SRex-BC Chen mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL); 21*3b994a75SRex-BC Chen mmio_write_32(MTK_WDT_INTERVAL, MTK_WDT_INTERVAL_VAL); 22*3b994a75SRex-BC Chen mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL); 23*3b994a75SRex-BC Chen mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL); 24*3b994a75SRex-BC Chen 25*3b994a75SRex-BC Chen /* Bit[2] = 0 (default=1), disable dfd apb bus protect_en */ 26*3b994a75SRex-BC Chen mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 0x1 << 2); 27*3b994a75SRex-BC Chen 28*3b994a75SRex-BC Chen /* Bit[0] : enable?mcusys_vproc?external_off?dfd?trigger -> 1 */ 29*3b994a75SRex-BC Chen mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); 30*3b994a75SRex-BC Chen 31*3b994a75SRex-BC Chen /* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */ 32*3b994a75SRex-BC Chen /* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */ 33*3b994a75SRex-BC Chen sync_writel(DFD_INTERNAL_CTL, 0x5); 34*3b994a75SRex-BC Chen 35*3b994a75SRex-BC Chen /* bit[13]: xreset_b_update_disable */ 36*3b994a75SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); 37*3b994a75SRex-BC Chen 38*3b994a75SRex-BC Chen /* 39*3b994a75SRex-BC Chen * bit[10:3]: DFD trigger selection mask 40*3b994a75SRex-BC Chen * bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger) 41*3b994a75SRex-BC Chen * bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger) 42*3b994a75SRex-BC Chen * bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger) 43*3b994a75SRex-BC Chen * bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger) 44*3b994a75SRex-BC Chen * bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger) 45*3b994a75SRex-BC Chen */ 46*3b994a75SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); 47*3b994a75SRex-BC Chen 48*3b994a75SRex-BC Chen /* 49*3b994a75SRex-BC Chen * bit[9] : rg_rw_dfd_trigger_sel[6] = 1(cpu_eb_sw_dfd_trigger) 50*3b994a75SRex-BC Chen * bit[10] : rg_rw_dfd_trigger_sel[7] = 1(cpu_eb_wdt_dfd_trigger) 51*3b994a75SRex-BC Chen */ 52*3b994a75SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); 53*3b994a75SRex-BC Chen 54*3b994a75SRex-BC Chen /* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */ 55*3b994a75SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); 56*3b994a75SRex-BC Chen 57*3b994a75SRex-BC Chen /* 58*3b994a75SRex-BC Chen * bit[0]: rg_rw_dfd_auto_power_on = 1 59*3b994a75SRex-BC Chen * bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us) 60*3b994a75SRex-BC Chen * bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us) 61*3b994a75SRex-BC Chen */ 62*3b994a75SRex-BC Chen mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); 63*3b994a75SRex-BC Chen 64*3b994a75SRex-BC Chen /* longest scan chain length */ 65*3b994a75SRex-BC Chen mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); 66*3b994a75SRex-BC Chen 67*3b994a75SRex-BC Chen /* bit[1:0]: rg_rw_dfd_shift_clock_ratio */ 68*3b994a75SRex-BC Chen mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); 69*3b994a75SRex-BC Chen 70*3b994a75SRex-BC Chen /* rg_dfd_test_so_over_64 */ 71*3b994a75SRex-BC Chen mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); 72*3b994a75SRex-BC Chen 73*3b994a75SRex-BC Chen /* DFD3.0 */ 74*3b994a75SRex-BC Chen mmio_write_32(DFD_TEST_SI_0, 0x0); 75*3b994a75SRex-BC Chen mmio_write_32(DFD_TEST_SI_1, 0x0); 76*3b994a75SRex-BC Chen mmio_write_32(DFD_TEST_SI_2, 0x0); 77*3b994a75SRex-BC Chen mmio_write_32(DFD_TEST_SI_3, 0x0); 78*3b994a75SRex-BC Chen 79*3b994a75SRex-BC Chen /* for iLDO feature */ 80*3b994a75SRex-BC Chen sync_writel(DFD_POWER_CTL, 0xF9); 81*3b994a75SRex-BC Chen 82*3b994a75SRex-BC Chen /* read offset */ 83*3b994a75SRex-BC Chen sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL); 84*3b994a75SRex-BC Chen 85*3b994a75SRex-BC Chen /* for DFD-3.0 setup */ 86*3b994a75SRex-BC Chen sync_writel(DFD_V30_CTL, 0xD); 87*3b994a75SRex-BC Chen 88*3b994a75SRex-BC Chen /* set base address */ 89*3b994a75SRex-BC Chen mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); 90*3b994a75SRex-BC Chen mmio_write_32(DFD_O_REG_0, 0); 91*3b994a75SRex-BC Chen 92*3b994a75SRex-BC Chen /* setup global variables for suspend and resume */ 93*3b994a75SRex-BC Chen dfd_enabled = true; 94*3b994a75SRex-BC Chen dfd_base_addr = base_addr; 95*3b994a75SRex-BC Chen dfd_chain_length = chain_length; 96*3b994a75SRex-BC Chen dfd_cache_dump = cache_dump; 97*3b994a75SRex-BC Chen 98*3b994a75SRex-BC Chen if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { 99*3b994a75SRex-BC Chen mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL); 100*3b994a75SRex-BC Chen sync_writel(DFD_V35_ENABLE, 0x1); 101*3b994a75SRex-BC Chen sync_writel(DFD_V35_TAP_NUMBER, 0xB); 102*3b994a75SRex-BC Chen sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); 103*3b994a75SRex-BC Chen sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); 104*3b994a75SRex-BC Chen 105*3b994a75SRex-BC Chen /* Cache dump only mode */ 106*3b994a75SRex-BC Chen sync_writel(DFD_V35_CTL, 0x1); 107*3b994a75SRex-BC Chen mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF); 108*3b994a75SRex-BC Chen mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL); 109*3b994a75SRex-BC Chen mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL); 110*3b994a75SRex-BC Chen mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL); 111*3b994a75SRex-BC Chen mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL); 112*3b994a75SRex-BC Chen 113*3b994a75SRex-BC Chen if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) { 114*3b994a75SRex-BC Chen sync_writel(DFD_HW_TRIGGER_MASK, 0xC); 115*3b994a75SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); 116*3b994a75SRex-BC Chen } 117*3b994a75SRex-BC Chen } 118*3b994a75SRex-BC Chen dsbsy(); 119*3b994a75SRex-BC Chen } 120*3b994a75SRex-BC Chen 121*3b994a75SRex-BC Chen void dfd_resume(void) 122*3b994a75SRex-BC Chen { 123*3b994a75SRex-BC Chen if (dfd_enabled == true) { 124*3b994a75SRex-BC Chen dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); 125*3b994a75SRex-BC Chen } 126*3b994a75SRex-BC Chen } 127*3b994a75SRex-BC Chen 128*3b994a75SRex-BC Chen uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, 129*3b994a75SRex-BC Chen uint64_t arg2, uint64_t arg3) 130*3b994a75SRex-BC Chen { 131*3b994a75SRex-BC Chen uint64_t ret = 0L; 132*3b994a75SRex-BC Chen 133*3b994a75SRex-BC Chen switch (arg0) { 134*3b994a75SRex-BC Chen case PLAT_MTK_DFD_SETUP_MAGIC: 135*3b994a75SRex-BC Chen INFO("[%s] DFD setup call from kernel\n", __func__); 136*3b994a75SRex-BC Chen dfd_setup(arg1, arg2, arg3); 137*3b994a75SRex-BC Chen break; 138*3b994a75SRex-BC Chen case PLAT_MTK_DFD_READ_MAGIC: 139*3b994a75SRex-BC Chen /* only allow to access DFD register base + 0x200 */ 140*3b994a75SRex-BC Chen if (arg1 <= 0x200) { 141*3b994a75SRex-BC Chen ret = mmio_read_32(MISC1_CFG_BASE + arg1); 142*3b994a75SRex-BC Chen } 143*3b994a75SRex-BC Chen break; 144*3b994a75SRex-BC Chen case PLAT_MTK_DFD_WRITE_MAGIC: 145*3b994a75SRex-BC Chen /* only allow to access DFD register base + 0x200 */ 146*3b994a75SRex-BC Chen if (arg1 <= 0x200) { 147*3b994a75SRex-BC Chen sync_writel(MISC1_CFG_BASE + arg1, arg2); 148*3b994a75SRex-BC Chen } 149*3b994a75SRex-BC Chen break; 150*3b994a75SRex-BC Chen default: 151*3b994a75SRex-BC Chen ret = MTK_SIP_E_INVALID_PARAM; 152*3b994a75SRex-BC Chen break; 153*3b994a75SRex-BC Chen } 154*3b994a75SRex-BC Chen 155*3b994a75SRex-BC Chen return ret; 156*3b994a75SRex-BC Chen } 157