1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 #include <lib/utils_def.h> 9 #include <mtk_dcm_utils.h> 10 11 #define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17)) 12 #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \ 13 BIT(16) | \ 14 BIT(17) | \ 15 BIT(18) | \ 16 BIT(21)) 17 #define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \ 18 BIT(16) | \ 19 BIT(17) | \ 20 BIT(18)) 21 #define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17)) 22 #define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \ 23 BIT(16) | \ 24 BIT(17) | \ 25 BIT(18) | \ 26 BIT(21)) 27 #define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \ 28 BIT(16) | \ 29 BIT(17) | \ 30 BIT(18)) 31 #define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17)) 32 #define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \ 33 (0x0 << 16) | \ 34 (0x0 << 17) | \ 35 (0x0 << 18) | \ 36 (0x0 << 21)) 37 #define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \ 38 (0x0 << 16) | \ 39 (0x0 << 17) | \ 40 (0x0 << 18)) 41 42 bool dcm_mp_cpusys_top_adb_dcm_is_on(void) 43 { 44 bool ret = true; 45 46 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) & 47 MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) == 48 (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON); 49 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) & 50 MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) == 51 (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON); 52 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & 53 MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) == 54 (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON); 55 56 return ret; 57 } 58 59 void dcm_mp_cpusys_top_adb_dcm(bool on) 60 { 61 if (on) { 62 /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */ 63 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, 64 MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, 65 MP_CPUSYS_TOP_ADB_DCM_REG0_ON); 66 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, 67 MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, 68 MP_CPUSYS_TOP_ADB_DCM_REG1_ON); 69 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 70 MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, 71 MP_CPUSYS_TOP_ADB_DCM_REG2_ON); 72 } else { 73 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */ 74 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, 75 MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, 76 MP_CPUSYS_TOP_ADB_DCM_REG0_OFF); 77 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, 78 MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, 79 MP_CPUSYS_TOP_ADB_DCM_REG1_OFF); 80 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 81 MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, 82 MP_CPUSYS_TOP_ADB_DCM_REG2_OFF); 83 } 84 } 85 86 #define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5)) 87 #define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8)) 88 #define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16)) 89 #define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5)) 90 #define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8)) 91 #define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16)) 92 #define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5)) 93 #define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8)) 94 #define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16)) 95 96 bool dcm_mp_cpusys_top_apb_dcm_is_on(void) 97 { 98 bool ret = true; 99 100 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & 101 MP_CPUSYS_TOP_APB_DCM_REG0_MASK) == 102 (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON); 103 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & 104 MP_CPUSYS_TOP_APB_DCM_REG1_MASK) == 105 (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON); 106 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & 107 MP_CPUSYS_TOP_APB_DCM_REG2_MASK) == 108 (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON); 109 110 return ret; 111 } 112 113 void dcm_mp_cpusys_top_apb_dcm(bool on) 114 { 115 if (on) { 116 /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */ 117 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 118 MP_CPUSYS_TOP_APB_DCM_REG0_MASK, 119 MP_CPUSYS_TOP_APB_DCM_REG0_ON); 120 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 121 MP_CPUSYS_TOP_APB_DCM_REG1_MASK, 122 MP_CPUSYS_TOP_APB_DCM_REG1_ON); 123 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, 124 MP_CPUSYS_TOP_APB_DCM_REG2_MASK, 125 MP_CPUSYS_TOP_APB_DCM_REG2_ON); 126 } else { 127 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */ 128 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 129 MP_CPUSYS_TOP_APB_DCM_REG0_MASK, 130 MP_CPUSYS_TOP_APB_DCM_REG0_OFF); 131 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 132 MP_CPUSYS_TOP_APB_DCM_REG1_MASK, 133 MP_CPUSYS_TOP_APB_DCM_REG1_OFF); 134 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, 135 MP_CPUSYS_TOP_APB_DCM_REG2_MASK, 136 MP_CPUSYS_TOP_APB_DCM_REG2_OFF); 137 } 138 } 139 140 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11) | \ 141 BIT(24) | \ 142 BIT(25)) 143 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11) | \ 144 BIT(24) | \ 145 BIT(25)) 146 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11) | \ 147 (0x0 << 24) | \ 148 (0x0 << 25)) 149 150 bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void) 151 { 152 bool ret = true; 153 154 ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) & 155 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) == 156 (unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); 157 158 return ret; 159 } 160 161 void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on) 162 { 163 if (on) { 164 /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ 165 mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 166 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, 167 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); 168 } else { 169 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ 170 mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 171 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, 172 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF); 173 } 174 } 175 176 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0)) 177 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0)) 178 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0)) 179 180 bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void) 181 { 182 bool ret = true; 183 184 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) & 185 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) == 186 (unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); 187 188 return ret; 189 } 190 191 void dcm_mp_cpusys_top_core_stall_dcm(bool on) 192 { 193 if (on) { 194 /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */ 195 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, 196 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, 197 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); 198 } else { 199 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */ 200 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, 201 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, 202 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF); 203 } 204 } 205 206 #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0)) 207 #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0)) 208 #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0)) 209 210 bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void) 211 { 212 bool ret = true; 213 214 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCSIC_DCM0) & 215 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) == 216 (unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); 217 218 return ret; 219 } 220 221 void dcm_mp_cpusys_top_cpubiu_dcm(bool on) 222 { 223 if (on) { 224 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */ 225 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, 226 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, 227 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); 228 } else { 229 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */ 230 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, 231 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, 232 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF); 233 } 234 } 235 236 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(24) | \ 237 BIT(25)) 238 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(24) | \ 239 BIT(25)) 240 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 24) | \ 241 (0x0 << 25)) 242 243 bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void) 244 { 245 bool ret = true; 246 247 ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) & 248 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) == 249 (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); 250 251 return ret; 252 } 253 254 void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on) 255 { 256 if (on) { 257 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ 258 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, 259 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, 260 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); 261 } else { 262 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ 263 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, 264 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, 265 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF); 266 } 267 } 268 269 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(24) | \ 270 BIT(25)) 271 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(24) | \ 272 BIT(25)) 273 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 24) | \ 274 (0x0 << 25)) 275 276 bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void) 277 { 278 bool ret = true; 279 280 ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) & 281 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) == 282 (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); 283 284 return ret; 285 } 286 287 void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on) 288 { 289 if (on) { 290 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ 291 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, 292 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, 293 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); 294 } else { 295 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ 296 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, 297 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, 298 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF); 299 } 300 } 301 302 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4)) 303 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4)) 304 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4)) 305 306 bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void) 307 { 308 bool ret = true; 309 310 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) & 311 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) == 312 (unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); 313 314 return ret; 315 } 316 317 void dcm_mp_cpusys_top_fcm_stall_dcm(bool on) 318 { 319 if (on) { 320 /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */ 321 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, 322 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, 323 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); 324 } else { 325 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */ 326 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, 327 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, 328 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF); 329 } 330 } 331 332 #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31)) 333 #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31)) 334 #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0U << 31)) 335 336 bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void) 337 { 338 bool ret = true; 339 340 ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) & 341 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) == 342 (unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); 343 344 return ret; 345 } 346 347 void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on) 348 { 349 if (on) { 350 /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ 351 mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 352 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, 353 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); 354 } else { 355 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ 356 mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 357 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, 358 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF); 359 } 360 } 361 362 #define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \ 363 BIT(4)) 364 #define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \ 365 BIT(4)) 366 #define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \ 367 (0x0 << 4)) 368 369 bool dcm_mp_cpusys_top_misc_dcm_is_on(void) 370 { 371 bool ret = true; 372 373 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & 374 MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) == 375 (unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON); 376 377 return ret; 378 } 379 380 void dcm_mp_cpusys_top_misc_dcm(bool on) 381 { 382 if (on) { 383 /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */ 384 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 385 MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, 386 MP_CPUSYS_TOP_MISC_DCM_REG0_ON); 387 } else { 388 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */ 389 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 390 MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, 391 MP_CPUSYS_TOP_MISC_DCM_REG0_OFF); 392 } 393 } 394 395 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3)) 396 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \ 397 BIT(1) | \ 398 BIT(2) | \ 399 BIT(3)) 400 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3)) 401 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \ 402 BIT(1) | \ 403 BIT(2) | \ 404 BIT(3)) 405 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3)) 406 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \ 407 (0x0 << 1) | \ 408 (0x0 << 2) | \ 409 (0x0 << 3)) 410 411 bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void) 412 { 413 bool ret = true; 414 415 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & 416 MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) == 417 (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); 418 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & 419 MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) == 420 (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON); 421 422 return ret; 423 } 424 425 void dcm_mp_cpusys_top_mp0_qdcm(bool on) 426 { 427 if (on) { 428 /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */ 429 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 430 MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, 431 MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); 432 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, 433 MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, 434 MP_CPUSYS_TOP_MP0_QDCM_REG1_ON); 435 } else { 436 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */ 437 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 438 MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, 439 MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF); 440 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, 441 MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, 442 MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF); 443 } 444 } 445 446 #define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \ 447 BIT(1) | \ 448 BIT(2) | \ 449 BIT(3)) 450 #define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \ 451 BIT(1) | \ 452 BIT(2) | \ 453 BIT(3)) 454 #define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \ 455 (0x0 << 1) | \ 456 (0x0 << 2) | \ 457 (0x0 << 3)) 458 459 bool dcm_cpccfg_reg_emi_wfifo_is_on(void) 460 { 461 bool ret = true; 462 463 ret &= ((mmio_read_32(CPCCFG_REG_EMI_WFIFO) & 464 CPCCFG_REG_EMI_WFIFO_REG0_MASK) == 465 (unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON); 466 467 return ret; 468 } 469 470 void dcm_cpccfg_reg_emi_wfifo(bool on) 471 { 472 if (on) { 473 /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */ 474 mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO, 475 CPCCFG_REG_EMI_WFIFO_REG0_MASK, 476 CPCCFG_REG_EMI_WFIFO_REG0_ON); 477 } else { 478 /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */ 479 mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO, 480 CPCCFG_REG_EMI_WFIFO_REG0_MASK, 481 CPCCFG_REG_EMI_WFIFO_REG0_OFF); 482 } 483 } 484