xref: /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h (revision 88906b443734399be5c07a5bd690b63d3d82cefa)
1*88906b44SFlora Fu /*
2*88906b44SFlora Fu  * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3*88906b44SFlora Fu  *
4*88906b44SFlora Fu  * SPDX-License-Identifier: BSD-3-Clause
5*88906b44SFlora Fu  */
6*88906b44SFlora Fu 
7*88906b44SFlora Fu #ifndef MTK_APUSYS_H
8*88906b44SFlora Fu #define MTK_APUSYS_H
9*88906b44SFlora Fu 
10*88906b44SFlora Fu #include <stdint.h>
11*88906b44SFlora Fu 
12*88906b44SFlora Fu /* setup the SMC command ops */
13*88906b44SFlora Fu #define MTK_SIP_APU_START_MCU	0x00U
14*88906b44SFlora Fu #define MTK_SIP_APU_STOP_MCU	0x01U
15*88906b44SFlora Fu 
16*88906b44SFlora Fu /* AO Register */
17*88906b44SFlora Fu #define AO_MD32_PRE_DEFINE	(APUSYS_APU_S_S_4_BASE + 0x00)
18*88906b44SFlora Fu #define AO_MD32_BOOT_CTRL	(APUSYS_APU_S_S_4_BASE + 0x04)
19*88906b44SFlora Fu #define AO_MD32_SYS_CTRL	(APUSYS_APU_S_S_4_BASE + 0x08)
20*88906b44SFlora Fu #define AO_SEC_FW		(APUSYS_APU_S_S_4_BASE + 0x10)
21*88906b44SFlora Fu #define AO_SEC_USR_FW		(APUSYS_APU_S_S_4_BASE + 0x14)
22*88906b44SFlora Fu 
23*88906b44SFlora Fu #define PRE_DEFINE_CACHE_TCM	0x3U
24*88906b44SFlora Fu #define PRE_DEFINE_CACHE	0x2U
25*88906b44SFlora Fu #define PRE_DEFINE_SHIFT_0G	0U
26*88906b44SFlora Fu #define PRE_DEFINE_SHIFT_1G	2U
27*88906b44SFlora Fu #define PRE_DEFINE_SHIFT_2G	4U
28*88906b44SFlora Fu #define PRE_DEFINE_SHIFT_3G	6U
29*88906b44SFlora Fu 
30*88906b44SFlora Fu #define SEC_FW_NON_SECURE	1U
31*88906b44SFlora Fu #define SEC_FW_SHIFT_NS		4U
32*88906b44SFlora Fu #define SEC_FW_DOMAIN_SHIFT	0U
33*88906b44SFlora Fu 
34*88906b44SFlora Fu #define SEC_USR_FW_NON_SECURE	1U
35*88906b44SFlora Fu #define SEC_USR_FW_SHIFT_NS	4U
36*88906b44SFlora Fu #define SEC_USR_FW_DOMAIN_SHIFT	0U
37*88906b44SFlora Fu 
38*88906b44SFlora Fu #define SYS_CTRL_RUN		0U
39*88906b44SFlora Fu #define SYS_CTRL_STALL		1U
40*88906b44SFlora Fu 
41*88906b44SFlora Fu /* Reviser Register */
42*88906b44SFlora Fu #define REVISER_SECUREFW_CTXT	(APUSYS_SCTRL_REVISER_BASE + 0x100)
43*88906b44SFlora Fu #define REVISER_USDRFW_CTXT	(APUSYS_SCTRL_REVISER_BASE + 0x104)
44*88906b44SFlora Fu 
45*88906b44SFlora Fu int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
46*88906b44SFlora Fu 			    uint32_t *ret1);
47*88906b44SFlora Fu #endif /* MTK_APUSYS_H */
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