188906b44SFlora Fu /* 288906b44SFlora Fu * Copyright (c) 2021, MediaTek Inc. All rights reserved. 388906b44SFlora Fu * 488906b44SFlora Fu * SPDX-License-Identifier: BSD-3-Clause 588906b44SFlora Fu */ 688906b44SFlora Fu 788906b44SFlora Fu #ifndef MTK_APUSYS_H 888906b44SFlora Fu #define MTK_APUSYS_H 988906b44SFlora Fu 1088906b44SFlora Fu #include <stdint.h> 1188906b44SFlora Fu 1288906b44SFlora Fu /* setup the SMC command ops */ 13*296b5902SFlora Fu #define MTK_SIP_APU_START_MCU (0x00U) 14*296b5902SFlora Fu #define MTK_SIP_APU_STOP_MCU (0x01U) 15*296b5902SFlora Fu #define MTK_SIP_APUPWR_BUS_PROT_CG_ON (0x02U) 16*296b5902SFlora Fu #define MTK_SIP_APUPWR_BULK_PLL (0x03U) 17*296b5902SFlora Fu #define MTK_SIP_APUPWR_ACC_INIT_ALL (0x04U) 18*296b5902SFlora Fu #define MTK_SIP_APUPWR_ACC_TOP (0x05U) 1988906b44SFlora Fu 2088906b44SFlora Fu /* AO Register */ 2188906b44SFlora Fu #define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00) 2288906b44SFlora Fu #define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04) 2388906b44SFlora Fu #define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08) 2488906b44SFlora Fu #define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10) 2588906b44SFlora Fu #define AO_SEC_USR_FW (APUSYS_APU_S_S_4_BASE + 0x14) 2688906b44SFlora Fu 27*296b5902SFlora Fu #define PRE_DEFINE_CACHE_TCM (0x3U) 28*296b5902SFlora Fu #define PRE_DEFINE_CACHE (0x2U) 29*296b5902SFlora Fu #define PRE_DEFINE_SHIFT_0G (0U) 30*296b5902SFlora Fu #define PRE_DEFINE_SHIFT_1G (2U) 31*296b5902SFlora Fu #define PRE_DEFINE_SHIFT_2G (4U) 32*296b5902SFlora Fu #define PRE_DEFINE_SHIFT_3G (6U) 3388906b44SFlora Fu 34*296b5902SFlora Fu #define SEC_FW_NON_SECURE (1U) 35*296b5902SFlora Fu #define SEC_FW_SHIFT_NS (4U) 36*296b5902SFlora Fu #define SEC_FW_DOMAIN_SHIFT (0U) 3788906b44SFlora Fu 38*296b5902SFlora Fu #define SEC_USR_FW_NON_SECURE (1U) 39*296b5902SFlora Fu #define SEC_USR_FW_SHIFT_NS (4U) 40*296b5902SFlora Fu #define SEC_USR_FW_DOMAIN_SHIFT (0U) 4188906b44SFlora Fu 42*296b5902SFlora Fu #define SYS_CTRL_RUN (0U) 43*296b5902SFlora Fu #define SYS_CTRL_STALL (1U) 4488906b44SFlora Fu 4588906b44SFlora Fu /* Reviser Register */ 4688906b44SFlora Fu #define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x100) 4788906b44SFlora Fu #define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x104) 4888906b44SFlora Fu 4988906b44SFlora Fu int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 5088906b44SFlora Fu uint32_t *ret1); 5188906b44SFlora Fu #endif /* MTK_APUSYS_H */ 52