1*88906b44SFlora Fu /* 2*88906b44SFlora Fu * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*88906b44SFlora Fu * 4*88906b44SFlora Fu * SPDX-License-Identifier: BSD-3-Clause 5*88906b44SFlora Fu */ 6*88906b44SFlora Fu 7*88906b44SFlora Fu #include <common/debug.h> 8*88906b44SFlora Fu #include <drivers/console.h> 9*88906b44SFlora Fu #include <lib/mmio.h> 10*88906b44SFlora Fu 11*88906b44SFlora Fu #include <mtk_apusys.h> 12*88906b44SFlora Fu #include <plat/common/platform.h> 13*88906b44SFlora Fu 14*88906b44SFlora Fu int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 15*88906b44SFlora Fu uint32_t *ret1) 16*88906b44SFlora Fu { 17*88906b44SFlora Fu int32_t ret = 0L; 18*88906b44SFlora Fu uint32_t request_ops; 19*88906b44SFlora Fu 20*88906b44SFlora Fu request_ops = (uint32_t)x1; 21*88906b44SFlora Fu 22*88906b44SFlora Fu switch (request_ops) { 23*88906b44SFlora Fu case MTK_SIP_APU_START_MCU: 24*88906b44SFlora Fu /* setup addr[33:32] in reviser */ 25*88906b44SFlora Fu mmio_write_32(REVISER_SECUREFW_CTXT, 0U); 26*88906b44SFlora Fu mmio_write_32(REVISER_USDRFW_CTXT, 0U); 27*88906b44SFlora Fu 28*88906b44SFlora Fu /* setup secure sideband */ 29*88906b44SFlora Fu mmio_write_32(AO_SEC_FW, 30*88906b44SFlora Fu (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) | 31*88906b44SFlora Fu (0U << SEC_FW_DOMAIN_SHIFT)); 32*88906b44SFlora Fu 33*88906b44SFlora Fu /* setup boot address */ 34*88906b44SFlora Fu mmio_write_32(AO_MD32_BOOT_CTRL, 0U); 35*88906b44SFlora Fu 36*88906b44SFlora Fu /* setup pre-define region */ 37*88906b44SFlora Fu mmio_write_32(AO_MD32_PRE_DEFINE, 38*88906b44SFlora Fu (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) | 39*88906b44SFlora Fu (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) | 40*88906b44SFlora Fu (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) | 41*88906b44SFlora Fu (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G)); 42*88906b44SFlora Fu 43*88906b44SFlora Fu /* release runstall */ 44*88906b44SFlora Fu mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN); 45*88906b44SFlora Fu 46*88906b44SFlora Fu INFO("[APUSYS] rev(0x%08x,0x%08x)\n", 47*88906b44SFlora Fu mmio_read_32(REVISER_SECUREFW_CTXT), 48*88906b44SFlora Fu mmio_read_32(REVISER_USDRFW_CTXT)); 49*88906b44SFlora Fu INFO("[APUSYS] ao(0x%08x,0x%08x,0x%08x,0x%08x,0x%08x)\n", 50*88906b44SFlora Fu mmio_read_32(AO_SEC_FW), 51*88906b44SFlora Fu mmio_read_32(AO_SEC_USR_FW), 52*88906b44SFlora Fu mmio_read_32(AO_MD32_BOOT_CTRL), 53*88906b44SFlora Fu mmio_read_32(AO_MD32_PRE_DEFINE), 54*88906b44SFlora Fu mmio_read_32(AO_MD32_SYS_CTRL)); 55*88906b44SFlora Fu break; 56*88906b44SFlora Fu case MTK_SIP_APU_STOP_MCU: 57*88906b44SFlora Fu /* hold runstall */ 58*88906b44SFlora Fu mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL); 59*88906b44SFlora Fu 60*88906b44SFlora Fu INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n", 61*88906b44SFlora Fu mmio_read_32(AO_MD32_BOOT_CTRL), 62*88906b44SFlora Fu mmio_read_32(AO_MD32_SYS_CTRL)); 63*88906b44SFlora Fu break; 64*88906b44SFlora Fu default: 65*88906b44SFlora Fu ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops); 66*88906b44SFlora Fu break; 67*88906b44SFlora Fu } 68*88906b44SFlora Fu 69*88906b44SFlora Fu return ret; 70*88906b44SFlora Fu } 71