1*174a1cfeSYidi Lin/* 2*174a1cfeSYidi Lin * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*174a1cfeSYidi Lin * 4*174a1cfeSYidi Lin * SPDX-License-Identifier: BSD-3-Clause 5*174a1cfeSYidi Lin */ 6*174a1cfeSYidi Lin 7*174a1cfeSYidi Lin#include <arch.h> 8*174a1cfeSYidi Lin#include <asm_macros.S> 9*174a1cfeSYidi Lin#include <platform_def.h> 10*174a1cfeSYidi Lin 11*174a1cfeSYidi Lin .globl plat_is_my_cpu_primary 12*174a1cfeSYidi Lin .globl plat_my_core_pos 13*174a1cfeSYidi Lin .globl plat_mediatek_calc_core_pos 14*174a1cfeSYidi Lin 15*174a1cfeSYidi Linfunc plat_is_my_cpu_primary 16*174a1cfeSYidi Lin mrs x0, mpidr_el1 17*174a1cfeSYidi Lin and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 18*174a1cfeSYidi Lin cmp x0, #PLAT_PRIMARY_CPU 19*174a1cfeSYidi Lin cset x0, eq 20*174a1cfeSYidi Lin ret 21*174a1cfeSYidi Linendfunc plat_is_my_cpu_primary 22*174a1cfeSYidi Lin 23*174a1cfeSYidi Lin /* ----------------------------------------------------- 24*174a1cfeSYidi Lin * unsigned int plat_my_core_pos(void) 25*174a1cfeSYidi Lin * This function uses the plat_mediatek_calc_core_pos() 26*174a1cfeSYidi Lin * definition to get the index of the calling CPU. 27*174a1cfeSYidi Lin * ----------------------------------------------------- 28*174a1cfeSYidi Lin */ 29*174a1cfeSYidi Linfunc plat_my_core_pos 30*174a1cfeSYidi Lin mrs x0, mpidr_el1 31*174a1cfeSYidi Lin b plat_mediatek_calc_core_pos 32*174a1cfeSYidi Linendfunc plat_my_core_pos 33*174a1cfeSYidi Lin 34*174a1cfeSYidi Lin /* ----------------------------------------------------- 35*174a1cfeSYidi Lin * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr); 36*174a1cfeSYidi Lin * 37*174a1cfeSYidi Lin * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and 38*174a1cfeSYidi Lin * AFF0 is thread id. There is only one cluster in ARMv8.2 39*174a1cfeSYidi Lin * and one thread in current implementation. 40*174a1cfeSYidi Lin * 41*174a1cfeSYidi Lin * With this function: CorePos = CoreID (AFF1) 42*174a1cfeSYidi Lin * we do it with x0 = (x0 >> 8) & 0xff 43*174a1cfeSYidi Lin * ----------------------------------------------------- 44*174a1cfeSYidi Lin */ 45*174a1cfeSYidi Linfunc plat_mediatek_calc_core_pos 46*174a1cfeSYidi Lin mov x1, #MPIDR_AFFLVL_MASK 47*174a1cfeSYidi Lin and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT 48*174a1cfeSYidi Lin ret 49*174a1cfeSYidi Linendfunc plat_mediatek_calc_core_pos 50