1f85f37d4SNina Wu# 2f85f37d4SNina Wu# Copyright (c) 2020, MediaTek Inc. All rights reserved. 3f85f37d4SNina Wu# 4f85f37d4SNina Wu# SPDX-License-Identifier: BSD-3-Clause 5f85f37d4SNina Wu# 6f85f37d4SNina Wu 7f85f37d4SNina WuMTK_PLAT := plat/mediatek 8f85f37d4SNina WuMTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} 9f85f37d4SNina Wu 10f85f37d4SNina WuPLAT_INCLUDES := -I${MTK_PLAT}/common/ \ 11*c63f1451Schristine.zhu -I${MTK_PLAT}/common/drivers/gic600/ \ 127e78300fSYidi Lin -I${MTK_PLAT}/common/drivers/uart/ \ 13cab49199SRoger Lu -I${MTK_PLAT}/common/lpm/ \ 14054af8f2SPo Xu -I${MTK_PLAT_SOC}/include/ \ 15054af8f2SPo Xu -I${MTK_PLAT_SOC}/drivers/ \ 1643d7bbccSNina Wu -I${MTK_PLAT_SOC}/drivers/dcm \ 1742f2fa82SXi Chen -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ 184a128018SDehui Sun -I${MTK_PLAT_SOC}/drivers/gpio/ \ 19271d9497SJames Liao -I${MTK_PLAT_SOC}/drivers/mcdi/ \ 20cbd6331bSHsin-Hsiung Wang -I${MTK_PLAT_SOC}/drivers/pmic/ \ 218709c939Selly.chiang -I${MTK_PLAT_SOC}/drivers/ptp3/ \ 22b686d330SYuchen Huang -I${MTK_PLAT_SOC}/drivers/rtc/ \ 233d1e536eSJames Liao -I${MTK_PLAT_SOC}/drivers/spmc/ \ 247e78300fSYidi Lin -I${MTK_PLAT_SOC}/drivers/timer/ 25f85f37d4SNina Wu 2674f72b13SGreta ZhangGICV3_SUPPORT_GIC600 := 1 27f85f37d4SNina Wuinclude drivers/arm/gic/v3/gicv3.mk 28f85f37d4SNina Wuinclude lib/xlat_tables_v2/xlat_tables.mk 29f85f37d4SNina Wu 30f85f37d4SNina WuPLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \ 31f85f37d4SNina Wu ${XLAT_TABLES_LIB_SRCS} \ 32f85f37d4SNina Wu plat/common/aarch64/crash_console_helpers.S \ 33f85f37d4SNina Wu plat/common/plat_psci_common.c 34f85f37d4SNina Wu 35f85f37d4SNina WuBL31_SOURCES += common/desc_image_load.c \ 3695cc8894SNina Wu drivers/delay_timer/delay_timer.c \ 3795cc8894SNina Wu drivers/delay_timer/generic_delay_timer.c \ 38f85f37d4SNina Wu drivers/ti/uart/aarch64/16550_console.S \ 39054af8f2SPo Xu drivers/gpio/gpio.c \ 40f85f37d4SNina Wu lib/bl_aux_params/bl_aux_params.c \ 41f85f37d4SNina Wu lib/cpus/aarch64/cortex_a55.S \ 42f85f37d4SNina Wu lib/cpus/aarch64/cortex_a76.S \ 43f85f37d4SNina Wu plat/common/plat_gicv3.c \ 44*c63f1451Schristine.zhu ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \ 45cbd6331bSHsin-Hsiung Wang ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \ 46b686d330SYuchen Huang ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ 47bb28dc7aSYuchen Huang ${MTK_PLAT}/common/drivers/uart/uart.c \ 48cab49199SRoger Lu ${MTK_PLAT}/common/lpm/mt_lp_rm.c \ 49f85f37d4SNina Wu ${MTK_PLAT}/common/mtk_plat_common.c \ 50189f038fSNina Wu ${MTK_PLAT}/common/mtk_sip_svc.c \ 51f85f37d4SNina Wu ${MTK_PLAT}/common/params_setup.c \ 52f85f37d4SNina Wu ${MTK_PLAT_SOC}/aarch64/platform_common.c \ 53f85f37d4SNina Wu ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ 54f85f37d4SNina Wu ${MTK_PLAT_SOC}/bl31_plat_setup.c \ 55cbd6331bSHsin-Hsiung Wang ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ 56b686d330SYuchen Huang ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ 57f85f37d4SNina Wu ${MTK_PLAT_SOC}/plat_pm.c \ 5874f72b13SGreta Zhang ${MTK_PLAT_SOC}/plat_topology.c \ 59b6cec337Sgtk_pangao ${MTK_PLAT_SOC}/plat_mt_cirq.c \ 60189f038fSNina Wu ${MTK_PLAT_SOC}/plat_sip_calls.c \ 6143d7bbccSNina Wu ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \ 6243d7bbccSNina Wu ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \ 6342f2fa82SXi Chen ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \ 644a128018SDehui Sun ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ 65271d9497SJames Liao ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \ 66271d9497SJames Liao ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \ 67df60025fSRoger Lu ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \ 68271d9497SJames Liao ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \ 698709c939Selly.chiang ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \ 703d1e536eSJames Liao ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ 714a128018SDehui Sun ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c 72f85f37d4SNina Wu 73ebb44440SRoger Lu# Build SPM drivers 74ebb44440SRoger Luinclude ${MTK_PLAT_SOC}/drivers/spm/build.mk 75ebb44440SRoger Lu 76f85f37d4SNina Wu# Configs for A76 and A55 77f85f37d4SNina WuHW_ASSISTED_COHERENCY := 1 78f85f37d4SNina WuUSE_COHERENT_MEM := 0 79f85f37d4SNina WuCTX_INCLUDE_AARCH32_REGS := 0 80f85f37d4SNina Wu 81f85f37d4SNina Wu# indicate the reset vector address can be programmed 82f85f37d4SNina WuPROGRAMMABLE_RESET_ADDRESS := 1 83f85f37d4SNina Wu 84f85f37d4SNina WuCOLD_BOOT_SINGLE_CPU := 1 85f85f37d4SNina Wu 86f85f37d4SNina WuMACH_MT8192 := 1 87f85f37d4SNina Wu$(eval $(call add_define,MACH_MT8192)) 88f85f37d4SNina Wu 89f85f37d4SNina Wuinclude lib/coreboot/coreboot.mk 90f85f37d4SNina Wu 91