1f85f37d4SNina Wu# 2f85f37d4SNina Wu# Copyright (c) 2020, MediaTek Inc. All rights reserved. 3f85f37d4SNina Wu# 4f85f37d4SNina Wu# SPDX-License-Identifier: BSD-3-Clause 5f85f37d4SNina Wu# 6f85f37d4SNina Wu 7f85f37d4SNina WuMTK_PLAT := plat/mediatek 8f85f37d4SNina WuMTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} 9f85f37d4SNina Wu 10f85f37d4SNina WuPLAT_INCLUDES := -I${MTK_PLAT}/common/ \ 11c63f1451Schristine.zhu -I${MTK_PLAT}/common/drivers/gic600/ \ 12aebd4dc8Smtk20895 -I${MTK_PLAT}/common/drivers/gpio/ \ 13*c52a10a2SYidi Lin -I${MTK_PLAT}/common/drivers/rtc/ \ 1446946036SYidi Lin -I${MTK_PLAT}/common/drivers/timer/ \ 157e78300fSYidi Lin -I${MTK_PLAT}/common/drivers/uart/ \ 16cab49199SRoger Lu -I${MTK_PLAT}/common/lpm/ \ 17054af8f2SPo Xu -I${MTK_PLAT_SOC}/include/ \ 18054af8f2SPo Xu -I${MTK_PLAT_SOC}/drivers/ \ 1943d7bbccSNina Wu -I${MTK_PLAT_SOC}/drivers/dcm \ 2042f2fa82SXi Chen -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ 214a128018SDehui Sun -I${MTK_PLAT_SOC}/drivers/gpio/ \ 22271d9497SJames Liao -I${MTK_PLAT_SOC}/drivers/mcdi/ \ 23cbd6331bSHsin-Hsiung Wang -I${MTK_PLAT_SOC}/drivers/pmic/ \ 248709c939Selly.chiang -I${MTK_PLAT_SOC}/drivers/ptp3/ \ 2546946036SYidi Lin -I${MTK_PLAT_SOC}/drivers/spmc/ 26f85f37d4SNina Wu 2774f72b13SGreta ZhangGICV3_SUPPORT_GIC600 := 1 28f85f37d4SNina Wuinclude drivers/arm/gic/v3/gicv3.mk 29f85f37d4SNina Wuinclude lib/xlat_tables_v2/xlat_tables.mk 30f85f37d4SNina Wu 31f85f37d4SNina WuPLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \ 32f85f37d4SNina Wu ${XLAT_TABLES_LIB_SRCS} \ 33f85f37d4SNina Wu plat/common/aarch64/crash_console_helpers.S \ 34f85f37d4SNina Wu plat/common/plat_psci_common.c 35f85f37d4SNina Wu 36f85f37d4SNina WuBL31_SOURCES += common/desc_image_load.c \ 3795cc8894SNina Wu drivers/delay_timer/delay_timer.c \ 3895cc8894SNina Wu drivers/delay_timer/generic_delay_timer.c \ 39f85f37d4SNina Wu drivers/ti/uart/aarch64/16550_console.S \ 40054af8f2SPo Xu drivers/gpio/gpio.c \ 41f85f37d4SNina Wu lib/bl_aux_params/bl_aux_params.c \ 42f85f37d4SNina Wu lib/cpus/aarch64/cortex_a55.S \ 43f85f37d4SNina Wu lib/cpus/aarch64/cortex_a76.S \ 44f85f37d4SNina Wu plat/common/plat_gicv3.c \ 45c63f1451Schristine.zhu ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \ 46aebd4dc8Smtk20895 ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \ 47cbd6331bSHsin-Hsiung Wang ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \ 48b686d330SYuchen Huang ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ 49*c52a10a2SYidi Lin ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c \ 5046946036SYidi Lin ${MTK_PLAT}/common/drivers/timer/mt_timer.c \ 51bb28dc7aSYuchen Huang ${MTK_PLAT}/common/drivers/uart/uart.c \ 52cab49199SRoger Lu ${MTK_PLAT}/common/lpm/mt_lp_rm.c \ 53e5490f95Sgtk_pangao ${MTK_PLAT}/common/mtk_cirq.c \ 54f85f37d4SNina Wu ${MTK_PLAT}/common/mtk_plat_common.c \ 55189f038fSNina Wu ${MTK_PLAT}/common/mtk_sip_svc.c \ 56f85f37d4SNina Wu ${MTK_PLAT}/common/params_setup.c \ 57f85f37d4SNina Wu ${MTK_PLAT_SOC}/aarch64/platform_common.c \ 58f85f37d4SNina Wu ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ 59f85f37d4SNina Wu ${MTK_PLAT_SOC}/bl31_plat_setup.c \ 60cbd6331bSHsin-Hsiung Wang ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ 61f85f37d4SNina Wu ${MTK_PLAT_SOC}/plat_pm.c \ 6274f72b13SGreta Zhang ${MTK_PLAT_SOC}/plat_topology.c \ 63189f038fSNina Wu ${MTK_PLAT_SOC}/plat_sip_calls.c \ 6443d7bbccSNina Wu ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \ 6543d7bbccSNina Wu ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \ 6642f2fa82SXi Chen ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \ 674a128018SDehui Sun ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ 68271d9497SJames Liao ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \ 69271d9497SJames Liao ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \ 70df60025fSRoger Lu ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \ 71271d9497SJames Liao ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \ 728709c939Selly.chiang ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \ 7346946036SYidi Lin ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c 74f85f37d4SNina Wu 75ebb44440SRoger Lu# Build SPM drivers 76ebb44440SRoger Luinclude ${MTK_PLAT_SOC}/drivers/spm/build.mk 77ebb44440SRoger Lu 78f85f37d4SNina Wu# Configs for A76 and A55 79f85f37d4SNina WuHW_ASSISTED_COHERENCY := 1 80f85f37d4SNina WuUSE_COHERENT_MEM := 0 81f85f37d4SNina WuCTX_INCLUDE_AARCH32_REGS := 0 82f85f37d4SNina Wu 83f85f37d4SNina Wu# indicate the reset vector address can be programmed 84f85f37d4SNina WuPROGRAMMABLE_RESET_ADDRESS := 1 85f85f37d4SNina Wu 86f85f37d4SNina WuCOLD_BOOT_SINGLE_CPU := 1 87f85f37d4SNina Wu 88f85f37d4SNina WuMACH_MT8192 := 1 89f85f37d4SNina Wu$(eval $(call add_define,MACH_MT8192)) 90f85f37d4SNina Wu 91f85f37d4SNina Wuinclude lib/coreboot/coreboot.mk 92f85f37d4SNina Wu 93