1f85f37d4SNina Wu# 2f85f37d4SNina Wu# Copyright (c) 2020, MediaTek Inc. All rights reserved. 3f85f37d4SNina Wu# 4f85f37d4SNina Wu# SPDX-License-Identifier: BSD-3-Clause 5f85f37d4SNina Wu# 6f85f37d4SNina Wu 7f85f37d4SNina WuMTK_PLAT := plat/mediatek 8f85f37d4SNina WuMTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} 9f85f37d4SNina Wu 10f85f37d4SNina WuPLAT_INCLUDES := -I${MTK_PLAT}/common/ \ 11054af8f2SPo Xu -I${MTK_PLAT_SOC}/include/ \ 12054af8f2SPo Xu -I${MTK_PLAT_SOC}/drivers/ \ 134a128018SDehui Sun -I${MTK_PLAT_SOC}/drivers/gpio/ \ 14271d9497SJames Liao -I${MTK_PLAT_SOC}/drivers/mcdi/ \ 15cbd6331bSHsin-Hsiung Wang -I${MTK_PLAT_SOC}/drivers/pmic/ \ 16*8709c939Selly.chiang -I${MTK_PLAT_SOC}/drivers/ptp3/ \ 173d1e536eSJames Liao -I${MTK_PLAT_SOC}/drivers/spmc/ \ 18bb28dc7aSYuchen Huang -I${MTK_PLAT_SOC}/drivers/timer/ \ 19bb28dc7aSYuchen Huang -I${MTK_PLAT_SOC}/drivers/uart/ 20f85f37d4SNina Wu 2174f72b13SGreta ZhangGICV3_SUPPORT_GIC600 := 1 22f85f37d4SNina Wuinclude drivers/arm/gic/v3/gicv3.mk 23f85f37d4SNina Wuinclude lib/xlat_tables_v2/xlat_tables.mk 24f85f37d4SNina Wu 25f85f37d4SNina WuPLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \ 26f85f37d4SNina Wu ${XLAT_TABLES_LIB_SRCS} \ 27f85f37d4SNina Wu plat/common/aarch64/crash_console_helpers.S \ 28f85f37d4SNina Wu plat/common/plat_psci_common.c 29f85f37d4SNina Wu 30f85f37d4SNina WuBL31_SOURCES += common/desc_image_load.c \ 3195cc8894SNina Wu drivers/delay_timer/delay_timer.c \ 3295cc8894SNina Wu drivers/delay_timer/generic_delay_timer.c \ 33f85f37d4SNina Wu drivers/ti/uart/aarch64/16550_console.S \ 34054af8f2SPo Xu drivers/gpio/gpio.c \ 35f85f37d4SNina Wu lib/bl_aux_params/bl_aux_params.c \ 36f85f37d4SNina Wu lib/cpus/aarch64/cortex_a55.S \ 37f85f37d4SNina Wu lib/cpus/aarch64/cortex_a76.S \ 38f85f37d4SNina Wu plat/common/plat_gicv3.c \ 39cbd6331bSHsin-Hsiung Wang ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \ 40bb28dc7aSYuchen Huang ${MTK_PLAT}/common/drivers/uart/uart.c \ 41f85f37d4SNina Wu ${MTK_PLAT}/common/mtk_plat_common.c \ 42189f038fSNina Wu ${MTK_PLAT}/common/mtk_sip_svc.c \ 43f85f37d4SNina Wu ${MTK_PLAT}/common/params_setup.c \ 44f85f37d4SNina Wu ${MTK_PLAT_SOC}/aarch64/platform_common.c \ 45f85f37d4SNina Wu ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ 46f85f37d4SNina Wu ${MTK_PLAT_SOC}/bl31_plat_setup.c \ 47cbd6331bSHsin-Hsiung Wang ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ 48f85f37d4SNina Wu ${MTK_PLAT_SOC}/plat_pm.c \ 4974f72b13SGreta Zhang ${MTK_PLAT_SOC}/plat_topology.c \ 50054af8f2SPo Xu ${MTK_PLAT_SOC}/plat_mt_gic.c \ 51b6cec337Sgtk_pangao ${MTK_PLAT_SOC}/plat_mt_cirq.c \ 52189f038fSNina Wu ${MTK_PLAT_SOC}/plat_sip_calls.c \ 534a128018SDehui Sun ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ 54271d9497SJames Liao ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \ 55271d9497SJames Liao ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \ 56271d9497SJames Liao ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \ 57*8709c939Selly.chiang ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \ 583d1e536eSJames Liao ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ 594a128018SDehui Sun ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c 60f85f37d4SNina Wu 61f85f37d4SNina Wu# Configs for A76 and A55 62f85f37d4SNina WuHW_ASSISTED_COHERENCY := 1 63f85f37d4SNina WuUSE_COHERENT_MEM := 0 64f85f37d4SNina WuCTX_INCLUDE_AARCH32_REGS := 0 65f85f37d4SNina Wu 66f85f37d4SNina Wu# indicate the reset vector address can be programmed 67f85f37d4SNina WuPROGRAMMABLE_RESET_ADDRESS := 1 68f85f37d4SNina Wu 69f85f37d4SNina WuCOLD_BOOT_SINGLE_CPU := 1 70f85f37d4SNina Wu 71f85f37d4SNina WuMACH_MT8192 := 1 72f85f37d4SNina Wu$(eval $(call add_define,MACH_MT8192)) 73f85f37d4SNina Wu 74f85f37d4SNina Wuinclude lib/coreboot/coreboot.mk 75f85f37d4SNina Wu 76