1f85f37d4SNina Wu# 2f85f37d4SNina Wu# Copyright (c) 2020, MediaTek Inc. All rights reserved. 3f85f37d4SNina Wu# 4f85f37d4SNina Wu# SPDX-License-Identifier: BSD-3-Clause 5f85f37d4SNina Wu# 6f85f37d4SNina Wu 7f85f37d4SNina WuMTK_PLAT := plat/mediatek 8f85f37d4SNina WuMTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} 9f85f37d4SNina Wu 10f85f37d4SNina WuPLAT_INCLUDES := -I${MTK_PLAT}/common/ \ 11054af8f2SPo Xu -I${MTK_PLAT_SOC}/include/ \ 12054af8f2SPo Xu -I${MTK_PLAT_SOC}/drivers/ \ 13*4a128018SDehui Sun -I${MTK_PLAT_SOC}/drivers/gpio/ \ 14*4a128018SDehui Sun -I${MTK_PLAT_SOC}/drivers/timer/ 15f85f37d4SNina Wu 1674f72b13SGreta ZhangGICV3_SUPPORT_GIC600 := 1 17f85f37d4SNina Wuinclude drivers/arm/gic/v3/gicv3.mk 18f85f37d4SNina Wuinclude lib/xlat_tables_v2/xlat_tables.mk 19f85f37d4SNina Wu 20f85f37d4SNina WuPLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \ 21f85f37d4SNina Wu ${XLAT_TABLES_LIB_SRCS} \ 22f85f37d4SNina Wu plat/common/aarch64/crash_console_helpers.S \ 23f85f37d4SNina Wu plat/common/plat_psci_common.c 24f85f37d4SNina Wu 25f85f37d4SNina WuBL31_SOURCES += common/desc_image_load.c \ 26f85f37d4SNina Wu drivers/ti/uart/aarch64/16550_console.S \ 27054af8f2SPo Xu drivers/gpio/gpio.c \ 28f85f37d4SNina Wu lib/bl_aux_params/bl_aux_params.c \ 29f85f37d4SNina Wu lib/cpus/aarch64/cortex_a55.S \ 30f85f37d4SNina Wu lib/cpus/aarch64/cortex_a76.S \ 31f85f37d4SNina Wu plat/common/plat_gicv3.c \ 32f85f37d4SNina Wu ${MTK_PLAT}/common/mtk_plat_common.c \ 33f85f37d4SNina Wu ${MTK_PLAT}/common/params_setup.c \ 34f85f37d4SNina Wu ${MTK_PLAT_SOC}/aarch64/platform_common.c \ 35f85f37d4SNina Wu ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ 36f85f37d4SNina Wu ${MTK_PLAT_SOC}/bl31_plat_setup.c \ 37f85f37d4SNina Wu ${MTK_PLAT_SOC}/plat_pm.c \ 3874f72b13SGreta Zhang ${MTK_PLAT_SOC}/plat_topology.c \ 39054af8f2SPo Xu ${MTK_PLAT_SOC}/plat_mt_gic.c \ 40b6cec337Sgtk_pangao ${MTK_PLAT_SOC}/plat_mt_cirq.c \ 41*4a128018SDehui Sun ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ 42*4a128018SDehui Sun ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c 43f85f37d4SNina Wu 44f85f37d4SNina Wu 45f85f37d4SNina Wu# Configs for A76 and A55 46f85f37d4SNina WuHW_ASSISTED_COHERENCY := 1 47f85f37d4SNina WuUSE_COHERENT_MEM := 0 48f85f37d4SNina WuCTX_INCLUDE_AARCH32_REGS := 0 49f85f37d4SNina Wu 50f85f37d4SNina Wu# indicate the reset vector address can be programmed 51f85f37d4SNina WuPROGRAMMABLE_RESET_ADDRESS := 1 52f85f37d4SNina Wu 53f85f37d4SNina WuCOLD_BOOT_SINGLE_CPU := 1 54f85f37d4SNina Wu 55f85f37d4SNina WuMACH_MT8192 := 1 56f85f37d4SNina Wu$(eval $(call add_define,MACH_MT8192)) 57f85f37d4SNina Wu 58f85f37d4SNina Wuinclude lib/coreboot/coreboot.mk 59f85f37d4SNina Wu 60