1*f85f37d4SNina Wu /* 2*f85f37d4SNina Wu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*f85f37d4SNina Wu * 4*f85f37d4SNina Wu * SPDX-License-Identifier: BSD-3-Clause 5*f85f37d4SNina Wu */ 6*f85f37d4SNina Wu 7*f85f37d4SNina Wu /* Project Includes */ 8*f85f37d4SNina Wu #include <arch.h> 9*f85f37d4SNina Wu #include <arch_helpers.h> 10*f85f37d4SNina Wu #include <lib/psci/psci.h> 11*f85f37d4SNina Wu 12*f85f37d4SNina Wu /* Platform Includes */ 13*f85f37d4SNina Wu #include <plat_helpers.h> 14*f85f37d4SNina Wu #include <platform_def.h> 15*f85f37d4SNina Wu 16*f85f37d4SNina Wu const unsigned char mtk_power_domain_tree_desc[] = { 17*f85f37d4SNina Wu /* Number of root nodes */ 18*f85f37d4SNina Wu PLATFORM_SYSTEM_COUNT, 19*f85f37d4SNina Wu /* Number of children for the root node */ 20*f85f37d4SNina Wu PLATFORM_CLUSTER_COUNT, 21*f85f37d4SNina Wu /* Number of children for the first cluster node */ 22*f85f37d4SNina Wu PLATFORM_CLUSTER0_CORE_COUNT, 23*f85f37d4SNina Wu }; 24*f85f37d4SNina Wu 25*f85f37d4SNina Wu /******************************************************************************* 26*f85f37d4SNina Wu * This function returns the MT8192 default topology tree information. 27*f85f37d4SNina Wu ******************************************************************************/ 28*f85f37d4SNina Wu const unsigned char *plat_get_power_domain_tree_desc(void) 29*f85f37d4SNina Wu { 30*f85f37d4SNina Wu return mtk_power_domain_tree_desc; 31*f85f37d4SNina Wu } 32*f85f37d4SNina Wu 33*f85f37d4SNina Wu /******************************************************************************* 34*f85f37d4SNina Wu * This function implements a part of the critical interface between the psci 35*f85f37d4SNina Wu * generic layer and the platform that allows the former to query the platform 36*f85f37d4SNina Wu * to convert an MPIDR to a unique linear index. An error code (-1) is returned 37*f85f37d4SNina Wu * in case the MPIDR is invalid. 38*f85f37d4SNina Wu ******************************************************************************/ 39*f85f37d4SNina Wu int plat_core_pos_by_mpidr(u_register_t mpidr) 40*f85f37d4SNina Wu { 41*f85f37d4SNina Wu unsigned int cluster_id, cpu_id; 42*f85f37d4SNina Wu 43*f85f37d4SNina Wu if (read_mpidr() & MPIDR_MT_MASK) { 44*f85f37d4SNina Wu /* ARMv8.2 arch */ 45*f85f37d4SNina Wu if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { 46*f85f37d4SNina Wu return -1; 47*f85f37d4SNina Wu } 48*f85f37d4SNina Wu return plat_mediatek_calc_core_pos(mpidr); 49*f85f37d4SNina Wu } 50*f85f37d4SNina Wu 51*f85f37d4SNina Wu mpidr &= MPIDR_AFFINITY_MASK; 52*f85f37d4SNina Wu 53*f85f37d4SNina Wu if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { 54*f85f37d4SNina Wu return -1; 55*f85f37d4SNina Wu } 56*f85f37d4SNina Wu 57*f85f37d4SNina Wu cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 58*f85f37d4SNina Wu cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 59*f85f37d4SNina Wu 60*f85f37d4SNina Wu if (cluster_id >= PLATFORM_CLUSTER_COUNT) { 61*f85f37d4SNina Wu return -1; 62*f85f37d4SNina Wu } 63*f85f37d4SNina Wu 64*f85f37d4SNina Wu /* 65*f85f37d4SNina Wu * Validate cpu_id by checking whether it represents a CPU in 66*f85f37d4SNina Wu * one of the two clusters present on the platform. 67*f85f37d4SNina Wu */ 68*f85f37d4SNina Wu if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { 69*f85f37d4SNina Wu return -1; 70*f85f37d4SNina Wu } 71*f85f37d4SNina Wu 72*f85f37d4SNina Wu return (cpu_id + (cluster_id * 8)); 73*f85f37d4SNina Wu } 74