1189f038fSNina Wu /* 2189f038fSNina Wu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3189f038fSNina Wu * 4189f038fSNina Wu * SPDX-License-Identifier: BSD-3-Clause 5189f038fSNina Wu */ 6189f038fSNina Wu 7189f038fSNina Wu #include <common/debug.h> 8189f038fSNina Wu #include <common/runtime_svc.h> 9*ca4c0c2eSFlora Fu #include <mtk_apusys.h> 10f3febccaSRoger Lu #include <mtk_sip_svc.h> 11f3febccaSRoger Lu #include <mt_spm_vcorefs.h> 12f3febccaSRoger Lu #include "plat_sip_calls.h" 13189f038fSNina Wu 14189f038fSNina Wu uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, 15189f038fSNina Wu u_register_t x1, 16189f038fSNina Wu u_register_t x2, 17189f038fSNina Wu u_register_t x3, 18189f038fSNina Wu u_register_t x4, 19189f038fSNina Wu void *cookie, 20189f038fSNina Wu void *handle, 21189f038fSNina Wu u_register_t flags) 22189f038fSNina Wu { 23f3febccaSRoger Lu uint64_t ret; 24*ca4c0c2eSFlora Fu uint32_t rnd_val0 = 0U; 25189f038fSNina Wu 26189f038fSNina Wu switch (smc_fid) { 27f3febccaSRoger Lu case MTK_SIP_VCORE_CONTROL_ARCH32: 28f3febccaSRoger Lu case MTK_SIP_VCORE_CONTROL_ARCH64: 29f3febccaSRoger Lu ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); 30f3febccaSRoger Lu SMC_RET2(handle, ret, x4); 31f3febccaSRoger Lu break; 32*ca4c0c2eSFlora Fu case MTK_SIP_APUSYS_CONTROL_AARCH32: 33*ca4c0c2eSFlora Fu case MTK_SIP_APUSYS_CONTROL_AARCH64: 34*ca4c0c2eSFlora Fu ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0); 35*ca4c0c2eSFlora Fu SMC_RET2(handle, ret, rnd_val0); 36*ca4c0c2eSFlora Fu break; 37189f038fSNina Wu default: 38189f038fSNina Wu ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 39189f038fSNina Wu break; 40189f038fSNina Wu } 41189f038fSNina Wu 42189f038fSNina Wu SMC_RET1(handle, SMC_UNK); 43189f038fSNina Wu } 44