xref: /rk3399_ARM-atf/plat/mediatek/mt8192/plat_sip_calls.c (revision 5340c5a041052dc3eee8b126a8bfad2d2de4e758)
1189f038fSNina Wu /*
2*2f3f5939SLeon Chen  * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
3189f038fSNina Wu  *
4189f038fSNina Wu  * SPDX-License-Identifier: BSD-3-Clause
5189f038fSNina Wu  */
6189f038fSNina Wu 
7189f038fSNina Wu #include <common/debug.h>
8189f038fSNina Wu #include <common/runtime_svc.h>
9ca4c0c2eSFlora Fu #include <mtk_apusys.h>
10f3febccaSRoger Lu #include <mtk_sip_svc.h>
11f3febccaSRoger Lu #include <mt_spm_vcorefs.h>
125183e637SRex-BC Chen #include <plat_dfd.h>
13f3febccaSRoger Lu #include "plat_sip_calls.h"
14189f038fSNina Wu 
mediatek_plat_sip_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)15189f038fSNina Wu uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
16189f038fSNina Wu 				u_register_t x1,
17189f038fSNina Wu 				u_register_t x2,
18189f038fSNina Wu 				u_register_t x3,
19189f038fSNina Wu 				u_register_t x4,
20189f038fSNina Wu 				void *cookie,
21189f038fSNina Wu 				void *handle,
22189f038fSNina Wu 				u_register_t flags)
23189f038fSNina Wu {
24f3febccaSRoger Lu 	uint64_t ret;
25ca4c0c2eSFlora Fu 	uint32_t rnd_val0 = 0U;
26189f038fSNina Wu 
27189f038fSNina Wu 	switch (smc_fid) {
28*2f3f5939SLeon Chen 	case MTK_SIP_VCORE_CONTROL_AARCH32:
29*2f3f5939SLeon Chen 	case MTK_SIP_VCORE_CONTROL_AARCH64:
30f3febccaSRoger Lu 		ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
31f3febccaSRoger Lu 		SMC_RET2(handle, ret, x4);
32f3febccaSRoger Lu 		break;
33ca4c0c2eSFlora Fu 	case MTK_SIP_APUSYS_CONTROL_AARCH32:
34ca4c0c2eSFlora Fu 	case MTK_SIP_APUSYS_CONTROL_AARCH64:
35ca4c0c2eSFlora Fu 		ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0);
36ca4c0c2eSFlora Fu 		SMC_RET2(handle, ret, rnd_val0);
37ca4c0c2eSFlora Fu 		break;
385183e637SRex-BC Chen 	case MTK_SIP_KERNEL_DFD_AARCH32:
395183e637SRex-BC Chen 	case MTK_SIP_KERNEL_DFD_AARCH64:
405183e637SRex-BC Chen 		ret = dfd_smc_dispatcher(x1, x2, x3, x4);
415183e637SRex-BC Chen 		SMC_RET1(handle, ret);
425183e637SRex-BC Chen 		break;
43189f038fSNina Wu 	default:
44189f038fSNina Wu 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
45189f038fSNina Wu 		break;
46189f038fSNina Wu 	}
47189f038fSNina Wu 
48189f038fSNina Wu 	SMC_RET1(handle, SMC_UNK);
49189f038fSNina Wu }
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