1 /* 2 * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* common headers */ 8 #include <assert.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/gpio.h> 13 #include <lib/psci/psci.h> 14 15 /* platform specific headers */ 16 #include <mt_gic_v3.h> 17 #include <mtk_ptp3_common.h> 18 #include <mtspmc.h> 19 #include <plat/common/platform.h> 20 #include <plat_dfd.h> 21 #include <plat_mtk_lpm.h> 22 #include <plat_params.h> 23 #include <plat_pm.h> 24 #include <pmic.h> 25 #include <rtc.h> 26 27 /* 28 * Cluster state request: 29 * [0] : The CPU requires cluster power down 30 * [1] : The CPU requires cluster power on 31 */ 32 #define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff) 33 #define coordinate_cluster_pwron() coordinate_cluster(1) 34 #define coordinate_cluster_pwroff() coordinate_cluster(0) 35 36 /* platform secure entry point */ 37 static uintptr_t secure_entrypoint; 38 /* per-CPU power state */ 39 static unsigned int plat_power_state[PLATFORM_CORE_COUNT]; 40 41 /* platform CPU power domain - ops */ 42 static const struct mt_lpm_tz *plat_mt_pm; 43 44 #define plat_mt_pm_invoke(_name, _cpu, _state) ({ \ 45 int ret = -1; \ 46 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ 47 ret = plat_mt_pm->_name(_cpu, _state); \ 48 } \ 49 ret; }) 50 51 #define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \ 52 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ 53 (void) plat_mt_pm->_name(_cpu, _state); \ 54 } \ 55 }) 56 57 /* 58 * Common MTK_platform operations to power on/off a 59 * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 60 */ 61 62 static void plat_cpu_pwrdwn_common(unsigned int cpu, 63 const psci_power_state_t *state, unsigned int req_pstate) 64 { 65 assert(cpu == plat_my_core_pos()); 66 67 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state); 68 69 if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) || 70 (req_pstate == 0U)) { /* hotplug off */ 71 coordinate_cluster_pwroff(); 72 } 73 74 /* Prevent interrupts from spuriously waking up this CPU */ 75 mt_gic_rdistif_save(); 76 gicv3_cpuif_disable(cpu); 77 gicv3_rdistif_off(cpu); 78 /* PTP3 config */ 79 ptp3_deinit(cpu); 80 } 81 82 static void plat_cpu_pwron_common(unsigned int cpu, 83 const psci_power_state_t *state, unsigned int req_pstate) 84 { 85 assert(cpu == plat_my_core_pos()); 86 87 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state); 88 89 coordinate_cluster_pwron(); 90 91 /* 92 * If mcusys does power down before then restore 93 * all CPUs' GIC Redistributors 94 */ 95 if (IS_MCUSYS_OFF_STATE(state)) { 96 mt_gic_rdistif_restore_all(); 97 } else { 98 gicv3_rdistif_on(cpu); 99 gicv3_cpuif_enable(cpu); 100 mt_gic_rdistif_init(); 101 mt_gic_rdistif_restore(); 102 } 103 104 /* PTP3 config */ 105 ptp3_init(cpu); 106 } 107 108 /* 109 * Common MTK_platform operations to power on/off a 110 * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 111 */ 112 113 static void plat_cluster_pwrdwn_common(unsigned int cpu, 114 const psci_power_state_t *state, unsigned int req_pstate) 115 { 116 assert(cpu == plat_my_core_pos()); 117 118 if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) { 119 coordinate_cluster_pwron(); 120 121 /* TODO: return on fail. 122 * Add a 'return' here before adding any code following 123 * the if-block. 124 */ 125 } 126 } 127 128 static void plat_cluster_pwron_common(unsigned int cpu, 129 const psci_power_state_t *state, unsigned int req_pstate) 130 { 131 assert(cpu == plat_my_core_pos()); 132 133 if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) { 134 /* TODO: return on fail. 135 * Add a 'return' here before adding any code following 136 * the if-block. 137 */ 138 } 139 } 140 141 /* 142 * Common MTK_platform operations to power on/off a 143 * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 144 */ 145 146 static void plat_mcusys_pwrdwn_common(unsigned int cpu, 147 const psci_power_state_t *state, unsigned int req_pstate) 148 { 149 assert(cpu == plat_my_core_pos()); 150 151 if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) { 152 return; /* return on fail */ 153 } 154 155 mt_gic_distif_save(); 156 gic_sgi_save_all(); 157 } 158 159 static void plat_mcusys_pwron_common(unsigned int cpu, 160 const psci_power_state_t *state, unsigned int req_pstate) 161 { 162 assert(cpu == plat_my_core_pos()); 163 164 if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) { 165 return; /* return on fail */ 166 } 167 168 mt_gic_init(); 169 mt_gic_distif_restore(); 170 gic_sgi_restore_all(); 171 172 dfd_resume(); 173 174 plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state); 175 } 176 177 /* 178 * plat_psci_ops implementation 179 */ 180 181 static void plat_cpu_standby(plat_local_state_t cpu_state) 182 { 183 uint64_t scr; 184 185 scr = read_scr_el3(); 186 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 187 188 isb(); 189 dsb(); 190 wfi(); 191 192 write_scr_el3(scr); 193 } 194 195 static int plat_power_domain_on(u_register_t mpidr) 196 { 197 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 198 unsigned int cluster = 0U; 199 200 if (cpu >= PLATFORM_CORE_COUNT) { 201 return PSCI_E_INVALID_PARAMS; 202 } 203 204 if (!spm_get_cluster_powerstate(cluster)) { 205 spm_poweron_cluster(cluster); 206 } 207 208 /* init CPU reset arch as AARCH64 */ 209 mcucfg_init_archstate(cluster, cpu, true); 210 mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); 211 spm_poweron_cpu(cluster, cpu); 212 213 return PSCI_E_SUCCESS; 214 } 215 216 static void plat_power_domain_on_finish(const psci_power_state_t *state) 217 { 218 unsigned long mpidr = read_mpidr_el1(); 219 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 220 221 assert(cpu < PLATFORM_CORE_COUNT); 222 223 /* Allow IRQs to wakeup this core in IDLE flow */ 224 mcucfg_enable_gic_wakeup(0U, cpu); 225 226 if (IS_CLUSTER_OFF_STATE(state)) { 227 plat_cluster_pwron_common(cpu, state, 0U); 228 } 229 230 plat_cpu_pwron_common(cpu, state, 0U); 231 } 232 233 static void plat_power_domain_off(const psci_power_state_t *state) 234 { 235 unsigned long mpidr = read_mpidr_el1(); 236 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 237 238 assert(cpu < PLATFORM_CORE_COUNT); 239 240 plat_cpu_pwrdwn_common(cpu, state, 0U); 241 spm_poweroff_cpu(0U, cpu); 242 243 /* prevent unintended IRQs from waking up the hot-unplugged core */ 244 mcucfg_disable_gic_wakeup(0U, cpu); 245 246 if (IS_CLUSTER_OFF_STATE(state)) { 247 plat_cluster_pwrdwn_common(cpu, state, 0U); 248 } 249 } 250 251 static void plat_power_domain_suspend(const psci_power_state_t *state) 252 { 253 unsigned int cpu = plat_my_core_pos(); 254 255 assert(cpu < PLATFORM_CORE_COUNT); 256 257 plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state); 258 259 /* Perform the common CPU specific operations */ 260 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]); 261 262 if (IS_CLUSTER_OFF_STATE(state)) { 263 /* Perform the common cluster specific operations */ 264 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]); 265 } 266 267 if (IS_MCUSYS_OFF_STATE(state)) { 268 /* Perform the common mcusys specific operations */ 269 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]); 270 } 271 } 272 273 static void plat_power_domain_suspend_finish(const psci_power_state_t *state) 274 { 275 unsigned int cpu = plat_my_core_pos(); 276 277 assert(cpu < PLATFORM_CORE_COUNT); 278 279 if (IS_MCUSYS_OFF_STATE(state)) { 280 /* Perform the common mcusys specific operations */ 281 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]); 282 } 283 284 if (IS_CLUSTER_OFF_STATE(state)) { 285 /* Perform the common cluster specific operations */ 286 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]); 287 } 288 289 /* Perform the common CPU specific operations */ 290 plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]); 291 292 plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state); 293 } 294 295 static int plat_validate_power_state(unsigned int power_state, 296 psci_power_state_t *req_state) 297 { 298 unsigned int pstate = psci_get_pstate_type(power_state); 299 unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state); 300 unsigned int cpu = plat_my_core_pos(); 301 302 if (pstate == PSTATE_TYPE_STANDBY) { 303 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE; 304 } else { 305 unsigned int i; 306 unsigned int pstate_id = psci_get_pstate_id(power_state); 307 plat_local_state_t s = MTK_LOCAL_STATE_OFF; 308 309 /* Use pstate_id to be power domain state */ 310 if (pstate_id > s) { 311 s = (plat_local_state_t)pstate_id; 312 } 313 314 for (i = 0U; i <= aff_lvl; i++) { 315 req_state->pwr_domain_state[i] = s; 316 } 317 } 318 319 plat_power_state[cpu] = power_state; 320 return PSCI_E_SUCCESS; 321 } 322 323 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) 324 { 325 unsigned int lv; 326 unsigned int cpu = plat_my_core_pos(); 327 328 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { 329 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE; 330 } 331 332 plat_power_state[cpu] = 333 psci_make_powerstate( 334 MT_PLAT_PWR_STATE_SYSTEM_SUSPEND, 335 PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL); 336 337 flush_dcache_range((uintptr_t) 338 &plat_power_state[cpu], 339 sizeof(plat_power_state[cpu])); 340 } 341 342 static void __dead2 plat_mtk_system_off(void) 343 { 344 INFO("MTK System Off\n"); 345 346 rtc_power_off_sequence(); 347 pmic_power_off(); 348 349 wfi(); 350 ERROR("MTK System Off: operation not handled.\n"); 351 panic(); 352 } 353 354 static void __dead2 plat_mtk_system_reset(void) 355 { 356 struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset(); 357 358 INFO("MTK System Reset\n"); 359 360 gpio_set_value(gpio_reset->index, gpio_reset->polarity); 361 362 wfi(); 363 ERROR("MTK System Reset: operation not handled.\n"); 364 panic(); 365 } 366 367 static const plat_psci_ops_t plat_psci_ops = { 368 .system_reset = plat_mtk_system_reset, 369 .cpu_standby = plat_cpu_standby, 370 .pwr_domain_on = plat_power_domain_on, 371 .pwr_domain_on_finish = plat_power_domain_on_finish, 372 .pwr_domain_off = plat_power_domain_off, 373 .pwr_domain_suspend = plat_power_domain_suspend, 374 .pwr_domain_suspend_finish = plat_power_domain_suspend_finish, 375 .system_off = plat_mtk_system_off, 376 .validate_power_state = plat_validate_power_state, 377 .get_sys_suspend_power_state = plat_get_sys_suspend_power_state 378 }; 379 380 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 381 const plat_psci_ops_t **psci_ops) 382 { 383 *psci_ops = &plat_psci_ops; 384 secure_entrypoint = sec_entrypoint; 385 386 /* 387 * init the warm reset config for boot CPU 388 * reset arch as AARCH64 389 * reset addr as function bl31_warm_entrypoint() 390 */ 391 mcucfg_init_archstate(0U, 0U, true); 392 mcucfg_set_bootaddr(0U, 0U, secure_entrypoint); 393 394 spmc_init(); 395 plat_mt_pm = mt_plat_cpu_pm_init(); 396 397 return 0; 398 } 399