1 /* 2 * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* common headers */ 8 #include <assert.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/gpio.h> 13 #include <lib/psci/psci.h> 14 15 /* platform specific headers */ 16 #include <mt_gic_v3.h> 17 #include <mtk_ptp3_common.h> 18 #include <mtspmc.h> 19 #include <plat/common/platform.h> 20 #include <plat_mtk_lpm.h> 21 #include <plat_params.h> 22 #include <plat_pm.h> 23 #include <pmic.h> 24 #include <rtc.h> 25 26 /* 27 * Cluster state request: 28 * [0] : The CPU requires cluster power down 29 * [1] : The CPU requires cluster power on 30 */ 31 #define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff) 32 #define coordinate_cluster_pwron() coordinate_cluster(1) 33 #define coordinate_cluster_pwroff() coordinate_cluster(0) 34 35 /* platform secure entry point */ 36 static uintptr_t secure_entrypoint; 37 /* per-CPU power state */ 38 static unsigned int plat_power_state[PLATFORM_CORE_COUNT]; 39 40 /* platform CPU power domain - ops */ 41 static const struct mt_lpm_tz *plat_mt_pm; 42 43 #define plat_mt_pm_invoke(_name, _cpu, _state) ({ \ 44 int ret = -1; \ 45 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ 46 ret = plat_mt_pm->_name(_cpu, _state); \ 47 } \ 48 ret; }) 49 50 #define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \ 51 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ 52 (void) plat_mt_pm->_name(_cpu, _state); \ 53 } \ 54 }) 55 56 /* 57 * Common MTK_platform operations to power on/off a 58 * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 59 */ 60 61 static void plat_cpu_pwrdwn_common(unsigned int cpu, 62 const psci_power_state_t *state, unsigned int req_pstate) 63 { 64 assert(cpu == plat_my_core_pos()); 65 66 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state); 67 68 if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) || 69 (req_pstate == 0U)) { /* hotplug off */ 70 coordinate_cluster_pwroff(); 71 } 72 73 /* Prevent interrupts from spuriously waking up this CPU */ 74 mt_gic_rdistif_save(); 75 gicv3_cpuif_disable(cpu); 76 gicv3_rdistif_off(cpu); 77 /* PTP3 config */ 78 ptp3_deinit(cpu); 79 } 80 81 static void plat_cpu_pwron_common(unsigned int cpu, 82 const psci_power_state_t *state, unsigned int req_pstate) 83 { 84 assert(cpu == plat_my_core_pos()); 85 86 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state); 87 88 coordinate_cluster_pwron(); 89 90 /* Enable the GIC CPU interface */ 91 gicv3_rdistif_on(cpu); 92 gicv3_cpuif_enable(cpu); 93 mt_gic_rdistif_init(); 94 95 /* 96 * If mcusys does power down before then restore 97 * all CPUs' GIC Redistributors 98 */ 99 if (IS_MCUSYS_OFF_STATE(state)) { 100 mt_gic_rdistif_restore_all(); 101 } else { 102 mt_gic_rdistif_restore(); 103 } 104 105 /* PTP3 config */ 106 ptp3_init(cpu); 107 } 108 109 /* 110 * Common MTK_platform operations to power on/off a 111 * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 112 */ 113 114 static void plat_cluster_pwrdwn_common(unsigned int cpu, 115 const psci_power_state_t *state, unsigned int req_pstate) 116 { 117 assert(cpu == plat_my_core_pos()); 118 119 if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) { 120 coordinate_cluster_pwron(); 121 122 /* TODO: return on fail. 123 * Add a 'return' here before adding any code following 124 * the if-block. 125 */ 126 } 127 } 128 129 static void plat_cluster_pwron_common(unsigned int cpu, 130 const psci_power_state_t *state, unsigned int req_pstate) 131 { 132 assert(cpu == plat_my_core_pos()); 133 134 if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) { 135 /* TODO: return on fail. 136 * Add a 'return' here before adding any code following 137 * the if-block. 138 */ 139 } 140 } 141 142 /* 143 * Common MTK_platform operations to power on/off a 144 * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 145 */ 146 147 static void plat_mcusys_pwrdwn_common(unsigned int cpu, 148 const psci_power_state_t *state, unsigned int req_pstate) 149 { 150 assert(cpu == plat_my_core_pos()); 151 152 if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) { 153 return; /* return on fail */ 154 } 155 156 mt_gic_distif_save(); 157 gic_sgi_save_all(); 158 } 159 160 static void plat_mcusys_pwron_common(unsigned int cpu, 161 const psci_power_state_t *state, unsigned int req_pstate) 162 { 163 assert(cpu == plat_my_core_pos()); 164 165 if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) { 166 return; /* return on fail */ 167 } 168 169 mt_gic_init(); 170 mt_gic_distif_restore(); 171 gic_sgi_restore_all(); 172 173 plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state); 174 } 175 176 /* 177 * plat_psci_ops implementation 178 */ 179 180 static void plat_cpu_standby(plat_local_state_t cpu_state) 181 { 182 uint64_t scr; 183 184 scr = read_scr_el3(); 185 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 186 187 isb(); 188 dsb(); 189 wfi(); 190 191 write_scr_el3(scr); 192 } 193 194 static int plat_power_domain_on(u_register_t mpidr) 195 { 196 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 197 unsigned int cluster = 0U; 198 199 if (cpu >= PLATFORM_CORE_COUNT) { 200 return PSCI_E_INVALID_PARAMS; 201 } 202 203 if (!spm_get_cluster_powerstate(cluster)) { 204 spm_poweron_cluster(cluster); 205 } 206 207 /* init CPU reset arch as AARCH64 */ 208 mcucfg_init_archstate(cluster, cpu, true); 209 mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); 210 spm_poweron_cpu(cluster, cpu); 211 212 return PSCI_E_SUCCESS; 213 } 214 215 static void plat_power_domain_on_finish(const psci_power_state_t *state) 216 { 217 unsigned long mpidr = read_mpidr_el1(); 218 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 219 220 assert(cpu < PLATFORM_CORE_COUNT); 221 222 /* Allow IRQs to wakeup this core in IDLE flow */ 223 mcucfg_enable_gic_wakeup(0U, cpu); 224 225 if (IS_CLUSTER_OFF_STATE(state)) { 226 plat_cluster_pwron_common(cpu, state, 0U); 227 } 228 229 plat_cpu_pwron_common(cpu, state, 0U); 230 } 231 232 static void plat_power_domain_off(const psci_power_state_t *state) 233 { 234 unsigned long mpidr = read_mpidr_el1(); 235 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 236 237 assert(cpu < PLATFORM_CORE_COUNT); 238 239 plat_cpu_pwrdwn_common(cpu, state, 0U); 240 spm_poweroff_cpu(0U, cpu); 241 242 /* prevent unintended IRQs from waking up the hot-unplugged core */ 243 mcucfg_disable_gic_wakeup(0U, cpu); 244 245 if (IS_CLUSTER_OFF_STATE(state)) { 246 plat_cluster_pwrdwn_common(cpu, state, 0U); 247 } 248 } 249 250 static void plat_power_domain_suspend(const psci_power_state_t *state) 251 { 252 unsigned int cpu = plat_my_core_pos(); 253 254 assert(cpu < PLATFORM_CORE_COUNT); 255 256 plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state); 257 258 /* Perform the common CPU specific operations */ 259 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]); 260 261 if (IS_CLUSTER_OFF_STATE(state)) { 262 /* Perform the common cluster specific operations */ 263 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]); 264 } 265 266 if (IS_MCUSYS_OFF_STATE(state)) { 267 /* Perform the common mcusys specific operations */ 268 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]); 269 } 270 } 271 272 static void plat_power_domain_suspend_finish(const psci_power_state_t *state) 273 { 274 unsigned int cpu = plat_my_core_pos(); 275 276 assert(cpu < PLATFORM_CORE_COUNT); 277 278 if (IS_MCUSYS_OFF_STATE(state)) { 279 /* Perform the common mcusys specific operations */ 280 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]); 281 } 282 283 if (IS_CLUSTER_OFF_STATE(state)) { 284 /* Perform the common cluster specific operations */ 285 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]); 286 } 287 288 /* Perform the common CPU specific operations */ 289 plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]); 290 291 plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state); 292 } 293 294 static int plat_validate_power_state(unsigned int power_state, 295 psci_power_state_t *req_state) 296 { 297 unsigned int pstate = psci_get_pstate_type(power_state); 298 unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state); 299 unsigned int cpu = plat_my_core_pos(); 300 301 if (pstate == PSTATE_TYPE_STANDBY) { 302 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE; 303 } else { 304 unsigned int i; 305 unsigned int pstate_id = psci_get_pstate_id(power_state); 306 plat_local_state_t s = MTK_LOCAL_STATE_OFF; 307 308 /* Use pstate_id to be power domain state */ 309 if (pstate_id > s) { 310 s = (plat_local_state_t)pstate_id; 311 } 312 313 for (i = 0U; i <= aff_lvl; i++) { 314 req_state->pwr_domain_state[i] = s; 315 } 316 } 317 318 plat_power_state[cpu] = power_state; 319 return PSCI_E_SUCCESS; 320 } 321 322 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) 323 { 324 unsigned int lv; 325 unsigned int cpu = plat_my_core_pos(); 326 327 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { 328 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE; 329 } 330 331 plat_power_state[cpu] = 332 psci_make_powerstate( 333 MT_PLAT_PWR_STATE_SYSTEM_SUSPEND, 334 PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL); 335 336 flush_dcache_range((uintptr_t) 337 &plat_power_state[cpu], 338 sizeof(plat_power_state[cpu])); 339 } 340 341 static void __dead2 plat_mtk_system_off(void) 342 { 343 INFO("MTK System Off\n"); 344 345 rtc_power_off_sequence(); 346 pmic_power_off(); 347 348 wfi(); 349 ERROR("MTK System Off: operation not handled.\n"); 350 panic(); 351 } 352 353 static void __dead2 plat_mtk_system_reset(void) 354 { 355 struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset(); 356 357 INFO("MTK System Reset\n"); 358 359 gpio_set_value(gpio_reset->index, gpio_reset->polarity); 360 361 wfi(); 362 ERROR("MTK System Reset: operation not handled.\n"); 363 panic(); 364 } 365 366 static const plat_psci_ops_t plat_psci_ops = { 367 .system_reset = plat_mtk_system_reset, 368 .cpu_standby = plat_cpu_standby, 369 .pwr_domain_on = plat_power_domain_on, 370 .pwr_domain_on_finish = plat_power_domain_on_finish, 371 .pwr_domain_off = plat_power_domain_off, 372 .pwr_domain_suspend = plat_power_domain_suspend, 373 .pwr_domain_suspend_finish = plat_power_domain_suspend_finish, 374 .system_off = plat_mtk_system_off, 375 .validate_power_state = plat_validate_power_state, 376 .get_sys_suspend_power_state = plat_get_sys_suspend_power_state 377 }; 378 379 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 380 const plat_psci_ops_t **psci_ops) 381 { 382 *psci_ops = &plat_psci_ops; 383 secure_entrypoint = sec_entrypoint; 384 385 /* 386 * init the warm reset config for boot CPU 387 * reset arch as AARCH64 388 * reset addr as function bl31_warm_entrypoint() 389 */ 390 mcucfg_init_archstate(0U, 0U, true); 391 mcucfg_set_bootaddr(0U, 0U, secure_entrypoint); 392 393 spmc_init(); 394 plat_mt_pm = mt_plat_cpu_pm_init(); 395 396 return 0; 397 } 398