1 /* 2 * Copyright (c) 2020-2024, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 11 #define PLAT_PRIMARY_CPU 0x0 12 13 #define MT_GIC_BASE 0x0c000000 14 #define PLAT_MT_CCI_BASE 0x0c500000 15 #define MCUCFG_BASE 0x0c530000 16 17 #define IO_PHYS 0x10000000 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE IO_PHYS 21 #define MTK_DEV_RNG0_SIZE 0x10000000 22 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000) 23 #define MTK_DEV_RNG1_SIZE 0x10000000 24 #define MTK_DEV_RNG2_BASE 0x0c000000 25 #define MTK_DEV_RNG2_SIZE 0x600000 26 #define MTK_MCDI_SRAM_BASE 0x11B000 27 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 28 29 #define APUSYS_BASE 0x19000000 30 #define APUSYS_SCTRL_REVISER_BASE 0x19021000 31 #define APUSYS_SCTRL_REVISER_SIZE 0x1000 32 #define APUSYS_APU_S_S_4_BASE 0x190F2000 33 #define APUSYS_APU_S_S_4_SIZE 0x1000 34 #define APUSYS_APC_AO_WRAPPER_BASE 0x190F8000 35 #define APUSYS_APC_AO_WRAPPER_SIZE 0x1000 36 #define APUSYS_NOC_DAPC_AO_BASE 0x190FC000 37 #define APUSYS_NOC_DAPC_AO_SIZE 0x1000 38 39 #define TOPCKGEN_BASE (IO_PHYS + 0x00000000) 40 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 41 #define GPIO_BASE (IO_PHYS + 0x00005000) 42 #define SPM_BASE (IO_PHYS + 0x00006000) 43 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 44 #define DVFSRC_BASE (IO_PHYS + 0x00012000) 45 #define PMIC_WRAP_BASE (IO_PHYS + 0x00026000) 46 #define DEVAPC_INFRA_AO_BASE (IO_PHYS + 0x00030000) 47 #define DEVAPC_PERI_AO_BASE (IO_PHYS + 0x00034000) 48 #define DEVAPC_PERI_AO2_BASE (IO_PHYS + 0x00038000) 49 #define DEVAPC_PERI_PAR_AO_BASE (IO_PHYS + 0x0003C000) 50 #define EMI_BASE (IO_PHYS + 0x00219000) 51 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) 52 #define SSPM_MBOX_BASE (IO_PHYS + 0x00480000) 53 #define IOCFG_RM_BASE (IO_PHYS + 0x01C20000) 54 #define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) 55 #define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) 56 #define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) 57 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 58 #define IOCFG_LB_BASE (IO_PHYS + 0x01E70000) 59 #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) 60 #define IOCFG_LT_BASE (IO_PHYS + 0x01F20000) 61 #define IOCFG_TL_BASE (IO_PHYS + 0x01F30000) 62 #define MMSYS_BASE (IO_PHYS + 0x04000000) 63 /******************************************************************************* 64 * UART related constants 65 ******************************************************************************/ 66 #define UART0_BASE (IO_PHYS + 0x01002000) 67 #define UART1_BASE (IO_PHYS + 0x01003000) 68 69 #define UART_BAUDRATE 115200 70 71 /******************************************************************************* 72 * System counter frequency related constants 73 ******************************************************************************/ 74 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 75 #define SYS_COUNTER_FREQ_IN_MHZ 13 76 77 /******************************************************************************* 78 * GIC-600 & interrupt handling related constants 79 ******************************************************************************/ 80 81 /* Base MTK_platform compatible GIC memory map */ 82 #define BASE_GICD_BASE MT_GIC_BASE 83 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 84 85 #define PLAT_MTK_G1S_IRQ_PROPS(grp) 86 87 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 88 #define CIRQ_REG_NUM 14 89 #define CIRQ_IRQ_NUM 439 90 #define CIRQ_SPI_START 64 91 #define MD_WDT_IRQ_BIT_ID 110 92 93 /******************************************************************************* 94 * Platform binary types for linking 95 ******************************************************************************/ 96 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 97 #define PLATFORM_LINKER_ARCH aarch64 98 99 /******************************************************************************* 100 * Generic platform constants 101 ******************************************************************************/ 102 #define PLATFORM_STACK_SIZE 0x800 103 104 #define PLAT_MAX_PWR_LVL U(3) 105 #define PLAT_MAX_RET_STATE U(1) 106 #define PLAT_MAX_OFF_STATE U(9) 107 108 #define PLATFORM_SYSTEM_COUNT U(1) 109 #define PLATFORM_MCUSYS_COUNT U(1) 110 #define PLATFORM_CLUSTER_COUNT U(1) 111 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 112 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 113 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 114 115 #define SOC_CHIP_ID U(0x8192) 116 117 /******************************************************************************* 118 * Platform memory map related constants 119 ******************************************************************************/ 120 #define TZRAM_BASE 0x54600000 121 #define TZRAM_SIZE 0x00030000 122 123 /******************************************************************************* 124 * BL31 specific defines. 125 ******************************************************************************/ 126 /* 127 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 128 * present). BL31_BASE is calculated using the current BL31 debug size plus a 129 * little space for growth. 130 */ 131 #define BL31_BASE (TZRAM_BASE + 0x1000) 132 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 133 134 /******************************************************************************* 135 * Platform specific page table and MMU setup constants 136 ******************************************************************************/ 137 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 138 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 139 #define MAX_XLAT_TABLES 16 140 #define MAX_MMAP_REGIONS 16 141 142 /******************************************************************************* 143 * Declarations and constants to access the mailboxes safely. Each mailbox is 144 * aligned on the biggest cache line size in the platform. This is known only 145 * to the platform as it might have a combination of integrated and external 146 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 147 * line at any cache level. They could belong to different cpus/clusters & 148 * get written while being protected by different locks causing corruption of 149 * a valid mailbox address. 150 ******************************************************************************/ 151 #define CACHE_WRITEBACK_SHIFT 6 152 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 153 #endif /* PLATFORM_DEF_H */ 154