1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 11 #define PLAT_PRIMARY_CPU 0x0 12 13 #define MT_GIC_BASE 0x0c000000 14 #define PLAT_MT_CCI_BASE 0x0c500000 15 #define MCUCFG_BASE 0x0c530000 16 17 #define IO_PHYS 0x10000000 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE IO_PHYS 21 #define MTK_DEV_RNG0_SIZE 0x10000000 22 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000) 23 #define MTK_DEV_RNG1_SIZE 0x10000000 24 #define MTK_DEV_RNG2_BASE 0x0c000000 25 #define MTK_DEV_RNG2_SIZE 0x600000 26 27 #define GPIO_BASE (IO_PHYS + 0x00005000) 28 #define SPM_BASE (IO_PHYS + 0x00006000) 29 #define IOCFG_RM_BASE (IO_PHYS + 0x01C20000) 30 #define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) 31 #define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) 32 #define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) 33 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 34 #define IOCFG_LB_BASE (IO_PHYS + 0x01E70000) 35 #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) 36 #define IOCFG_LT_BASE (IO_PHYS + 0x01F20000) 37 #define IOCFG_TL_BASE (IO_PHYS + 0x01F30000) 38 /******************************************************************************* 39 * UART related constants 40 ******************************************************************************/ 41 #define UART0_BASE (IO_PHYS + 0x01002000) 42 #define UART1_BASE (IO_PHYS + 0x01003000) 43 44 #define UART_BAUDRATE 115200 45 46 /******************************************************************************* 47 * System counter frequency related constants 48 ******************************************************************************/ 49 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 50 #define SYS_COUNTER_FREQ_IN_MHZ 13 51 52 /******************************************************************************* 53 * GIC-400 & interrupt handling related constants 54 ******************************************************************************/ 55 56 /* Base MTK_platform compatible GIC memory map */ 57 #define BASE_GICD_BASE MT_GIC_BASE 58 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 59 60 /******************************************************************************* 61 * Platform binary types for linking 62 ******************************************************************************/ 63 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 64 #define PLATFORM_LINKER_ARCH aarch64 65 66 /******************************************************************************* 67 * Generic platform constants 68 ******************************************************************************/ 69 #define PLATFORM_STACK_SIZE 0x800 70 71 #define PLAT_MAX_PWR_LVL U(2) 72 #define PLAT_MAX_RET_STATE U(1) 73 #define PLAT_MAX_OFF_STATE U(2) 74 75 #define PLATFORM_SYSTEM_COUNT U(1) 76 #define PLATFORM_CLUSTER_COUNT U(1) 77 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 78 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 79 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 80 81 #define SOC_CHIP_ID U(0x8192) 82 83 /******************************************************************************* 84 * Platform memory map related constants 85 ******************************************************************************/ 86 #define TZRAM_BASE 0x54600000 87 #define TZRAM_SIZE 0x00030000 88 89 /******************************************************************************* 90 * BL31 specific defines. 91 ******************************************************************************/ 92 /* 93 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 94 * present). BL31_BASE is calculated using the current BL31 debug size plus a 95 * little space for growth. 96 */ 97 #define BL31_BASE (TZRAM_BASE + 0x1000) 98 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 99 100 /******************************************************************************* 101 * Platform specific page table and MMU setup constants 102 ******************************************************************************/ 103 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 104 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 105 #define MAX_XLAT_TABLES 16 106 #define MAX_MMAP_REGIONS 16 107 108 /******************************************************************************* 109 * Declarations and constants to access the mailboxes safely. Each mailbox is 110 * aligned on the biggest cache line size in the platform. This is known only 111 * to the platform as it might have a combination of integrated and external 112 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 113 * line at any cache level. They could belong to different cpus/clusters & 114 * get written while being protected by different locks causing corruption of 115 * a valid mailbox address. 116 ******************************************************************************/ 117 #define CACHE_WRITEBACK_SHIFT 6 118 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 119 #endif /* PLATFORM_DEF_H */ 120