1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 11 #define PLAT_PRIMARY_CPU 0x0 12 13 #define MT_GIC_BASE 0x0c000000 14 #define PLAT_MT_CCI_BASE 0x0c500000 15 #define MCUCFG_BASE 0x0c530000 16 17 #define IO_PHYS 0x10000000 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE IO_PHYS 21 #define MTK_DEV_RNG0_SIZE 0x10000000 22 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000) 23 #define MTK_DEV_RNG1_SIZE 0x10000000 24 #define MTK_DEV_RNG2_BASE 0x0c000000 25 #define MTK_DEV_RNG2_SIZE 0x600000 26 27 /******************************************************************************* 28 * UART related constants 29 ******************************************************************************/ 30 #define UART0_BASE (IO_PHYS + 0x01002000) 31 #define UART1_BASE (IO_PHYS + 0x01003000) 32 33 #define UART_BAUDRATE 115200 34 35 /******************************************************************************* 36 * System counter frequency related constants 37 ******************************************************************************/ 38 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 39 #define SYS_COUNTER_FREQ_IN_MHZ 13 40 41 /******************************************************************************* 42 * Platform binary types for linking 43 ******************************************************************************/ 44 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 45 #define PLATFORM_LINKER_ARCH aarch64 46 47 /******************************************************************************* 48 * Generic platform constants 49 ******************************************************************************/ 50 #define PLATFORM_STACK_SIZE 0x800 51 52 #define PLAT_MAX_PWR_LVL U(2) 53 #define PLAT_MAX_RET_STATE U(1) 54 #define PLAT_MAX_OFF_STATE U(2) 55 56 #define PLATFORM_SYSTEM_COUNT U(1) 57 #define PLATFORM_CLUSTER_COUNT U(1) 58 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 59 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 60 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 61 62 #define SOC_CHIP_ID U(0x8192) 63 64 /******************************************************************************* 65 * Platform memory map related constants 66 ******************************************************************************/ 67 #define TZRAM_BASE 0x54600000 68 #define TZRAM_SIZE 0x00030000 69 70 /******************************************************************************* 71 * BL31 specific defines. 72 ******************************************************************************/ 73 /* 74 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 75 * present). BL31_BASE is calculated using the current BL31 debug size plus a 76 * little space for growth. 77 */ 78 #define BL31_BASE (TZRAM_BASE + 0x1000) 79 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 80 81 /******************************************************************************* 82 * Platform specific page table and MMU setup constants 83 ******************************************************************************/ 84 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 85 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 86 #define MAX_XLAT_TABLES 16 87 #define MAX_MMAP_REGIONS 16 88 89 /******************************************************************************* 90 * Declarations and constants to access the mailboxes safely. Each mailbox is 91 * aligned on the biggest cache line size in the platform. This is known only 92 * to the platform as it might have a combination of integrated and external 93 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 94 * line at any cache level. They could belong to different cpus/clusters & 95 * get written while being protected by different locks causing corruption of 96 * a valid mailbox address. 97 ******************************************************************************/ 98 #define CACHE_WRITEBACK_SHIFT 6 99 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 100 #endif /* PLATFORM_DEF_H */ 101