1*f85f37d4SNina Wu /* 2*f85f37d4SNina Wu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*f85f37d4SNina Wu * 4*f85f37d4SNina Wu * SPDX-License-Identifier: BSD-3-Clause 5*f85f37d4SNina Wu */ 6*f85f37d4SNina Wu 7*f85f37d4SNina Wu #ifndef PLATFORM_DEF_H 8*f85f37d4SNina Wu #define PLATFORM_DEF_H 9*f85f37d4SNina Wu 10*f85f37d4SNina Wu 11*f85f37d4SNina Wu #define PLAT_PRIMARY_CPU 0x0 12*f85f37d4SNina Wu 13*f85f37d4SNina Wu #define MT_GIC_BASE 0x0c000000 14*f85f37d4SNina Wu #define PLAT_MT_CCI_BASE 0x0c500000 15*f85f37d4SNina Wu #define MCUCFG_BASE 0x0c530000 16*f85f37d4SNina Wu 17*f85f37d4SNina Wu #define IO_PHYS 0x10000000 18*f85f37d4SNina Wu 19*f85f37d4SNina Wu /* Aggregate of all devices for MMU mapping */ 20*f85f37d4SNina Wu #define MTK_DEV_RNG0_BASE IO_PHYS 21*f85f37d4SNina Wu #define MTK_DEV_RNG0_SIZE 0x10000000 22*f85f37d4SNina Wu #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000) 23*f85f37d4SNina Wu #define MTK_DEV_RNG1_SIZE 0x10000000 24*f85f37d4SNina Wu #define MTK_DEV_RNG2_BASE 0x0c000000 25*f85f37d4SNina Wu #define MTK_DEV_RNG2_SIZE 0x600000 26*f85f37d4SNina Wu 27*f85f37d4SNina Wu /******************************************************************************* 28*f85f37d4SNina Wu * UART related constants 29*f85f37d4SNina Wu ******************************************************************************/ 30*f85f37d4SNina Wu #define UART0_BASE (IO_PHYS + 0x01002000) 31*f85f37d4SNina Wu #define UART1_BASE (IO_PHYS + 0x01003000) 32*f85f37d4SNina Wu 33*f85f37d4SNina Wu #define UART_BAUDRATE 115200 34*f85f37d4SNina Wu 35*f85f37d4SNina Wu /******************************************************************************* 36*f85f37d4SNina Wu * System counter frequency related constants 37*f85f37d4SNina Wu ******************************************************************************/ 38*f85f37d4SNina Wu #define SYS_COUNTER_FREQ_IN_TICKS 13000000 39*f85f37d4SNina Wu #define SYS_COUNTER_FREQ_IN_MHZ 13 40*f85f37d4SNina Wu 41*f85f37d4SNina Wu /******************************************************************************* 42*f85f37d4SNina Wu * Platform binary types for linking 43*f85f37d4SNina Wu ******************************************************************************/ 44*f85f37d4SNina Wu #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 45*f85f37d4SNina Wu #define PLATFORM_LINKER_ARCH aarch64 46*f85f37d4SNina Wu 47*f85f37d4SNina Wu /******************************************************************************* 48*f85f37d4SNina Wu * Generic platform constants 49*f85f37d4SNina Wu ******************************************************************************/ 50*f85f37d4SNina Wu #define PLATFORM_STACK_SIZE 0x800 51*f85f37d4SNina Wu 52*f85f37d4SNina Wu #define PLAT_MAX_PWR_LVL U(2) 53*f85f37d4SNina Wu #define PLAT_MAX_RET_STATE U(1) 54*f85f37d4SNina Wu #define PLAT_MAX_OFF_STATE U(2) 55*f85f37d4SNina Wu 56*f85f37d4SNina Wu #define PLATFORM_SYSTEM_COUNT U(1) 57*f85f37d4SNina Wu #define PLATFORM_CLUSTER_COUNT U(1) 58*f85f37d4SNina Wu #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 59*f85f37d4SNina Wu #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 60*f85f37d4SNina Wu #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 61*f85f37d4SNina Wu 62*f85f37d4SNina Wu /******************************************************************************* 63*f85f37d4SNina Wu * Platform memory map related constants 64*f85f37d4SNina Wu ******************************************************************************/ 65*f85f37d4SNina Wu #define TZRAM_BASE 0x54600000 66*f85f37d4SNina Wu #define TZRAM_SIZE 0x00030000 67*f85f37d4SNina Wu 68*f85f37d4SNina Wu /******************************************************************************* 69*f85f37d4SNina Wu * BL31 specific defines. 70*f85f37d4SNina Wu ******************************************************************************/ 71*f85f37d4SNina Wu /* 72*f85f37d4SNina Wu * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 73*f85f37d4SNina Wu * present). BL31_BASE is calculated using the current BL31 debug size plus a 74*f85f37d4SNina Wu * little space for growth. 75*f85f37d4SNina Wu */ 76*f85f37d4SNina Wu #define BL31_BASE (TZRAM_BASE + 0x1000) 77*f85f37d4SNina Wu #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 78*f85f37d4SNina Wu 79*f85f37d4SNina Wu /******************************************************************************* 80*f85f37d4SNina Wu * Platform specific page table and MMU setup constants 81*f85f37d4SNina Wu ******************************************************************************/ 82*f85f37d4SNina Wu #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 83*f85f37d4SNina Wu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 84*f85f37d4SNina Wu #define MAX_XLAT_TABLES 16 85*f85f37d4SNina Wu #define MAX_MMAP_REGIONS 16 86*f85f37d4SNina Wu 87*f85f37d4SNina Wu /******************************************************************************* 88*f85f37d4SNina Wu * Declarations and constants to access the mailboxes safely. Each mailbox is 89*f85f37d4SNina Wu * aligned on the biggest cache line size in the platform. This is known only 90*f85f37d4SNina Wu * to the platform as it might have a combination of integrated and external 91*f85f37d4SNina Wu * caches. Such alignment ensures that two maiboxes do not sit on the same cache 92*f85f37d4SNina Wu * line at any cache level. They could belong to different cpus/clusters & 93*f85f37d4SNina Wu * get written while being protected by different locks causing corruption of 94*f85f37d4SNina Wu * a valid mailbox address. 95*f85f37d4SNina Wu ******************************************************************************/ 96*f85f37d4SNina Wu #define CACHE_WRITEBACK_SHIFT 6 97*f85f37d4SNina Wu #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 98*f85f37d4SNina Wu #endif /* PLATFORM_DEF_H */ 99