1f85f37d4SNina Wu /* 2f85f37d4SNina Wu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3f85f37d4SNina Wu * 4f85f37d4SNina Wu * SPDX-License-Identifier: BSD-3-Clause 5f85f37d4SNina Wu */ 6f85f37d4SNina Wu 7f85f37d4SNina Wu #ifndef PLATFORM_DEF_H 8f85f37d4SNina Wu #define PLATFORM_DEF_H 9f85f37d4SNina Wu 10f85f37d4SNina Wu 11f85f37d4SNina Wu #define PLAT_PRIMARY_CPU 0x0 12f85f37d4SNina Wu 13f85f37d4SNina Wu #define MT_GIC_BASE 0x0c000000 14f85f37d4SNina Wu #define PLAT_MT_CCI_BASE 0x0c500000 15f85f37d4SNina Wu #define MCUCFG_BASE 0x0c530000 16f85f37d4SNina Wu 17f85f37d4SNina Wu #define IO_PHYS 0x10000000 18f85f37d4SNina Wu 19f85f37d4SNina Wu /* Aggregate of all devices for MMU mapping */ 20f85f37d4SNina Wu #define MTK_DEV_RNG0_BASE IO_PHYS 21f85f37d4SNina Wu #define MTK_DEV_RNG0_SIZE 0x10000000 22f85f37d4SNina Wu #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000) 23f85f37d4SNina Wu #define MTK_DEV_RNG1_SIZE 0x10000000 24f85f37d4SNina Wu #define MTK_DEV_RNG2_BASE 0x0c000000 25f85f37d4SNina Wu #define MTK_DEV_RNG2_SIZE 0x600000 26f85f37d4SNina Wu 27f85f37d4SNina Wu /******************************************************************************* 28f85f37d4SNina Wu * UART related constants 29f85f37d4SNina Wu ******************************************************************************/ 30f85f37d4SNina Wu #define UART0_BASE (IO_PHYS + 0x01002000) 31f85f37d4SNina Wu #define UART1_BASE (IO_PHYS + 0x01003000) 32f85f37d4SNina Wu 33f85f37d4SNina Wu #define UART_BAUDRATE 115200 34f85f37d4SNina Wu 35f85f37d4SNina Wu /******************************************************************************* 36f85f37d4SNina Wu * System counter frequency related constants 37f85f37d4SNina Wu ******************************************************************************/ 38f85f37d4SNina Wu #define SYS_COUNTER_FREQ_IN_TICKS 13000000 39f85f37d4SNina Wu #define SYS_COUNTER_FREQ_IN_MHZ 13 40f85f37d4SNina Wu 41f85f37d4SNina Wu /******************************************************************************* 42f85f37d4SNina Wu * Platform binary types for linking 43f85f37d4SNina Wu ******************************************************************************/ 44f85f37d4SNina Wu #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 45f85f37d4SNina Wu #define PLATFORM_LINKER_ARCH aarch64 46f85f37d4SNina Wu 47f85f37d4SNina Wu /******************************************************************************* 48f85f37d4SNina Wu * Generic platform constants 49f85f37d4SNina Wu ******************************************************************************/ 50f85f37d4SNina Wu #define PLATFORM_STACK_SIZE 0x800 51f85f37d4SNina Wu 52f85f37d4SNina Wu #define PLAT_MAX_PWR_LVL U(2) 53f85f37d4SNina Wu #define PLAT_MAX_RET_STATE U(1) 54f85f37d4SNina Wu #define PLAT_MAX_OFF_STATE U(2) 55f85f37d4SNina Wu 56f85f37d4SNina Wu #define PLATFORM_SYSTEM_COUNT U(1) 57f85f37d4SNina Wu #define PLATFORM_CLUSTER_COUNT U(1) 58f85f37d4SNina Wu #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 59f85f37d4SNina Wu #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 60f85f37d4SNina Wu #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 61f85f37d4SNina Wu 62*74a34600SHsin-Yi Wang #define SOC_CHIP_ID U(0x8192) 63*74a34600SHsin-Yi Wang 64f85f37d4SNina Wu /******************************************************************************* 65f85f37d4SNina Wu * Platform memory map related constants 66f85f37d4SNina Wu ******************************************************************************/ 67f85f37d4SNina Wu #define TZRAM_BASE 0x54600000 68f85f37d4SNina Wu #define TZRAM_SIZE 0x00030000 69f85f37d4SNina Wu 70f85f37d4SNina Wu /******************************************************************************* 71f85f37d4SNina Wu * BL31 specific defines. 72f85f37d4SNina Wu ******************************************************************************/ 73f85f37d4SNina Wu /* 74f85f37d4SNina Wu * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 75f85f37d4SNina Wu * present). BL31_BASE is calculated using the current BL31 debug size plus a 76f85f37d4SNina Wu * little space for growth. 77f85f37d4SNina Wu */ 78f85f37d4SNina Wu #define BL31_BASE (TZRAM_BASE + 0x1000) 79f85f37d4SNina Wu #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 80f85f37d4SNina Wu 81f85f37d4SNina Wu /******************************************************************************* 82f85f37d4SNina Wu * Platform specific page table and MMU setup constants 83f85f37d4SNina Wu ******************************************************************************/ 84f85f37d4SNina Wu #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 85f85f37d4SNina Wu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 86f85f37d4SNina Wu #define MAX_XLAT_TABLES 16 87f85f37d4SNina Wu #define MAX_MMAP_REGIONS 16 88f85f37d4SNina Wu 89f85f37d4SNina Wu /******************************************************************************* 90f85f37d4SNina Wu * Declarations and constants to access the mailboxes safely. Each mailbox is 91f85f37d4SNina Wu * aligned on the biggest cache line size in the platform. This is known only 92f85f37d4SNina Wu * to the platform as it might have a combination of integrated and external 93f85f37d4SNina Wu * caches. Such alignment ensures that two maiboxes do not sit on the same cache 94f85f37d4SNina Wu * line at any cache level. They could belong to different cpus/clusters & 95f85f37d4SNina Wu * get written while being protected by different locks causing corruption of 96f85f37d4SNina Wu * a valid mailbox address. 97f85f37d4SNina Wu ******************************************************************************/ 98f85f37d4SNina Wu #define CACHE_WRITEBACK_SHIFT 6 99f85f37d4SNina Wu #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 100f85f37d4SNina Wu #endif /* PLATFORM_DEF_H */ 101