1*ebb44440SRoger Lu /* 2*ebb44440SRoger Lu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*ebb44440SRoger Lu * 4*ebb44440SRoger Lu * SPDX-License-Identifier: BSD-3-Clause 5*ebb44440SRoger Lu */ 6*ebb44440SRoger Lu 7*ebb44440SRoger Lu #ifndef MT_SPM_RESOURCE_REQ_H 8*ebb44440SRoger Lu #define MT_SPM_RESOURCE_REQ_H 9*ebb44440SRoger Lu 10*ebb44440SRoger Lu /* SPM resource request internal bit */ 11*ebb44440SRoger Lu #define MT_SPM_BIT_XO_FPM 0 12*ebb44440SRoger Lu #define MT_SPM_BIT_26M 1 13*ebb44440SRoger Lu #define MT_SPM_BIT_INFRA 2 14*ebb44440SRoger Lu #define MT_SPM_BIT_SYSPLL 3 15*ebb44440SRoger Lu #define MT_SPM_BIT_DRAM_S0 4 16*ebb44440SRoger Lu #define MT_SPM_BIT_DRAM_S1 5 17*ebb44440SRoger Lu 18*ebb44440SRoger Lu /* SPM resource request internal bit_mask */ 19*ebb44440SRoger Lu #define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM) 20*ebb44440SRoger Lu #define MT_SPM_26M BIT(MT_SPM_BIT_26M) 21*ebb44440SRoger Lu #define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA) 22*ebb44440SRoger Lu #define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL) 23*ebb44440SRoger Lu #define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0) 24*ebb44440SRoger Lu #define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1) 25*ebb44440SRoger Lu #endif /* MT_SPM_RESOURCE_REQ_H */ 26