1 /* 2 * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <lib/mmio.h> 9 10 #include <mt_spm.h> 11 #include <mt_spm_conservation.h> 12 #include <mt_spm_idle.h> 13 #include <mt_spm_internal.h> 14 #include <mt_spm_reg.h> 15 #include <mt_spm_resource_req.h> 16 #include <plat_pm.h> 17 18 #define __WAKE_SRC_FOR_IDLE_COMMON__ \ 19 (R12_PCM_TIMER | \ 20 R12_KP_IRQ_B | \ 21 R12_APWDT_EVENT_B | \ 22 R12_APXGPT1_EVENT_B | \ 23 R12_CONN2AP_SPM_WAKEUP_B | \ 24 R12_EINT_EVENT_B | \ 25 R12_CONN_WDT_IRQ_B | \ 26 R12_CCIF0_EVENT_B | \ 27 R12_SSPM2SPM_WAKEUP_B | \ 28 R12_SCP2SPM_WAKEUP_B | \ 29 R12_ADSP2SPM_WAKEUP_B | \ 30 R12_USBX_CDSC_B | \ 31 R12_USBX_POWERDWN_B | \ 32 R12_SYS_TIMER_EVENT_B | \ 33 R12_EINT_EVENT_SECURE_B | \ 34 R12_CCIF1_EVENT_B | \ 35 R12_AFE_IRQ_MCU_B | \ 36 R12_SYS_CIRQ_IRQ_B | \ 37 R12_MD2AP_PEER_EVENT_B | \ 38 R12_MD1_WDT_B | \ 39 R12_CLDMA_EVENT_B | \ 40 R12_REG_CPU_WAKEUP | \ 41 R12_APUSYS_WAKE_HOST_B | \ 42 R12_PCIE_BRIDGE_IRQ | \ 43 R12_PCIE_IRQ) 44 45 #if defined(CFG_MICROTRUST_TEE_SUPPORT) 46 #define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__) 47 #else 48 #define WAKE_SRC_FOR_IDLE \ 49 (__WAKE_SRC_FOR_IDLE_COMMON__ | \ 50 R12_SEJ_EVENT_B) 51 #endif 52 53 static struct pwr_ctrl idle_spm_pwr = { 54 .timer_val = 0x28000, 55 .wake_src = WAKE_SRC_FOR_IDLE, 56 57 /* Auto-gen Start */ 58 59 /* SPM_AP_STANDBY_CON */ 60 .reg_wfi_op = 0, 61 .reg_wfi_type = 0, 62 .reg_mp0_cputop_idle_mask = 0, 63 .reg_mp1_cputop_idle_mask = 0, 64 .reg_mcusys_idle_mask = 0, 65 .reg_md_apsrc_1_sel = 0, 66 .reg_md_apsrc_0_sel = 0, 67 .reg_conn_apsrc_sel = 0, 68 69 /* SPM_SRC6_MASK */ 70 .reg_dpmaif_srcclkena_mask_b = 1, 71 .reg_dpmaif_infra_req_mask_b = 1, 72 .reg_dpmaif_apsrc_req_mask_b = 1, 73 .reg_dpmaif_vrf18_req_mask_b = 1, 74 .reg_dpmaif_ddr_en_mask_b = 1, 75 76 /* SPM_SRC_REQ */ 77 .reg_spm_apsrc_req = 1, 78 .reg_spm_f26m_req = 1, 79 .reg_spm_infra_req = 1, 80 .reg_spm_vrf18_req = 1, 81 .reg_spm_ddr_en_req = 1, 82 .reg_spm_dvfs_req = 0, 83 .reg_spm_sw_mailbox_req = 0, 84 .reg_spm_sspm_mailbox_req = 0, 85 .reg_spm_adsp_mailbox_req = 0, 86 .reg_spm_scp_mailbox_req = 0, 87 88 /* SPM_SRC_MASK */ 89 .reg_md_srcclkena_0_mask_b = 1, 90 .reg_md_srcclkena2infra_req_0_mask_b = 0, 91 .reg_md_apsrc2infra_req_0_mask_b = 1, 92 .reg_md_apsrc_req_0_mask_b = 1, 93 .reg_md_vrf18_req_0_mask_b = 1, 94 .reg_md_ddr_en_0_mask_b = 1, 95 .reg_md_srcclkena_1_mask_b = 0, 96 .reg_md_srcclkena2infra_req_1_mask_b = 0, 97 .reg_md_apsrc2infra_req_1_mask_b = 0, 98 .reg_md_apsrc_req_1_mask_b = 0, 99 .reg_md_vrf18_req_1_mask_b = 0, 100 .reg_md_ddr_en_1_mask_b = 0, 101 .reg_conn_srcclkena_mask_b = 1, 102 .reg_conn_srcclkenb_mask_b = 0, 103 .reg_conn_infra_req_mask_b = 1, 104 .reg_conn_apsrc_req_mask_b = 1, 105 .reg_conn_vrf18_req_mask_b = 1, 106 .reg_conn_ddr_en_mask_b = 1, 107 .reg_conn_vfe28_mask_b = 0, 108 .reg_srcclkeni0_srcclkena_mask_b = 1, 109 .reg_srcclkeni0_infra_req_mask_b = 1, 110 .reg_srcclkeni1_srcclkena_mask_b = 0, 111 .reg_srcclkeni1_infra_req_mask_b = 0, 112 .reg_srcclkeni2_srcclkena_mask_b = 0, 113 .reg_srcclkeni2_infra_req_mask_b = 0, 114 .reg_infrasys_apsrc_req_mask_b = 0, 115 .reg_infrasys_ddr_en_mask_b = 1, 116 .reg_md32_srcclkena_mask_b = 1, 117 .reg_md32_infra_req_mask_b = 1, 118 .reg_md32_apsrc_req_mask_b = 1, 119 .reg_md32_vrf18_req_mask_b = 1, 120 .reg_md32_ddr_en_mask_b = 1, 121 122 /* SPM_SRC2_MASK */ 123 .reg_scp_srcclkena_mask_b = 1, 124 .reg_scp_infra_req_mask_b = 1, 125 .reg_scp_apsrc_req_mask_b = 1, 126 .reg_scp_vrf18_req_mask_b = 1, 127 .reg_scp_ddr_en_mask_b = 1, 128 .reg_audio_dsp_srcclkena_mask_b = 1, 129 .reg_audio_dsp_infra_req_mask_b = 1, 130 .reg_audio_dsp_apsrc_req_mask_b = 1, 131 .reg_audio_dsp_vrf18_req_mask_b = 1, 132 .reg_audio_dsp_ddr_en_mask_b = 1, 133 .reg_ufs_srcclkena_mask_b = 1, 134 .reg_ufs_infra_req_mask_b = 1, 135 .reg_ufs_apsrc_req_mask_b = 1, 136 .reg_ufs_vrf18_req_mask_b = 1, 137 .reg_ufs_ddr_en_mask_b = 1, 138 .reg_disp0_apsrc_req_mask_b = 1, 139 .reg_disp0_ddr_en_mask_b = 1, 140 .reg_disp1_apsrc_req_mask_b = 1, 141 .reg_disp1_ddr_en_mask_b = 1, 142 .reg_gce_infra_req_mask_b = 1, 143 .reg_gce_apsrc_req_mask_b = 1, 144 .reg_gce_vrf18_req_mask_b = 1, 145 .reg_gce_ddr_en_mask_b = 1, 146 .reg_apu_srcclkena_mask_b = 1, 147 .reg_apu_infra_req_mask_b = 1, 148 .reg_apu_apsrc_req_mask_b = 1, 149 .reg_apu_vrf18_req_mask_b = 1, 150 .reg_apu_ddr_en_mask_b = 1, 151 .reg_cg_check_srcclkena_mask_b = 0, 152 .reg_cg_check_apsrc_req_mask_b = 0, 153 .reg_cg_check_vrf18_req_mask_b = 0, 154 .reg_cg_check_ddr_en_mask_b = 0, 155 156 /* SPM_SRC3_MASK */ 157 .reg_dvfsrc_event_trigger_mask_b = 1, 158 .reg_sw2spm_int0_mask_b = 0, 159 .reg_sw2spm_int1_mask_b = 0, 160 .reg_sw2spm_int2_mask_b = 0, 161 .reg_sw2spm_int3_mask_b = 0, 162 .reg_sc_adsp2spm_wakeup_mask_b = 0, 163 .reg_sc_sspm2spm_wakeup_mask_b = 0, 164 .reg_sc_scp2spm_wakeup_mask_b = 0, 165 .reg_csyspwrreq_mask = 1, 166 .reg_spm_srcclkena_reserved_mask_b = 0, 167 .reg_spm_infra_req_reserved_mask_b = 0, 168 .reg_spm_apsrc_req_reserved_mask_b = 0, 169 .reg_spm_vrf18_req_reserved_mask_b = 0, 170 .reg_spm_ddr_en_reserved_mask_b = 0, 171 .reg_mcupm_srcclkena_mask_b = 1, 172 .reg_mcupm_infra_req_mask_b = 1, 173 .reg_mcupm_apsrc_req_mask_b = 1, 174 .reg_mcupm_vrf18_req_mask_b = 1, 175 .reg_mcupm_ddr_en_mask_b = 1, 176 .reg_msdc0_srcclkena_mask_b = 1, 177 .reg_msdc0_infra_req_mask_b = 1, 178 .reg_msdc0_apsrc_req_mask_b = 1, 179 .reg_msdc0_vrf18_req_mask_b = 1, 180 .reg_msdc0_ddr_en_mask_b = 1, 181 .reg_msdc1_srcclkena_mask_b = 1, 182 .reg_msdc1_infra_req_mask_b = 1, 183 .reg_msdc1_apsrc_req_mask_b = 1, 184 .reg_msdc1_vrf18_req_mask_b = 1, 185 .reg_msdc1_ddr_en_mask_b = 1, 186 187 /* SPM_SRC4_MASK */ 188 .ccif_event_mask_b = 0xFFF, 189 .reg_bak_psri_srcclkena_mask_b = 0, 190 .reg_bak_psri_infra_req_mask_b = 0, 191 .reg_bak_psri_apsrc_req_mask_b = 0, 192 .reg_bak_psri_vrf18_req_mask_b = 0, 193 .reg_bak_psri_ddr_en_mask_b = 0, 194 .reg_dramc0_md32_infra_req_mask_b = 1, 195 .reg_dramc0_md32_vrf18_req_mask_b = 0, 196 .reg_dramc1_md32_infra_req_mask_b = 1, 197 .reg_dramc1_md32_vrf18_req_mask_b = 0, 198 .reg_conn_srcclkenb2pwrap_mask_b = 0, 199 .reg_dramc0_md32_wakeup_mask = 1, 200 .reg_dramc1_md32_wakeup_mask = 1, 201 202 /* SPM_SRC5_MASK */ 203 .reg_mcusys_merge_apsrc_req_mask_b = 0x11, 204 .reg_mcusys_merge_ddr_en_mask_b = 0x11, 205 .reg_msdc2_srcclkena_mask_b = 1, 206 .reg_msdc2_infra_req_mask_b = 1, 207 .reg_msdc2_apsrc_req_mask_b = 1, 208 .reg_msdc2_vrf18_req_mask_b = 1, 209 .reg_msdc2_ddr_en_mask_b = 1, 210 .reg_pcie_srcclkena_mask_b = 1, 211 .reg_pcie_infra_req_mask_b = 1, 212 .reg_pcie_apsrc_req_mask_b = 1, 213 .reg_pcie_vrf18_req_mask_b = 1, 214 .reg_pcie_ddr_en_mask_b = 1, 215 216 /* SPM_WAKEUP_EVENT_MASK */ 217 .reg_wakeup_event_mask = 0x01282202, 218 219 /* SPM_WAKEUP_EVENT_EXT_MASK */ 220 .reg_ext_wakeup_event_mask = 0xFFFFFFFF, 221 222 /* Auto-gen End */ 223 }; 224 225 struct spm_lp_scen idle_spm_lp = { 226 .pwrctrl = &idle_spm_pwr, 227 }; 228 229 int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, 230 spm_idle_conduct fn) 231 { 232 unsigned int src_req = 0; 233 234 if (fn != NULL) { 235 fn(&idle_spm_lp, &src_req); 236 } 237 238 return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req); 239 } 240 void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand, 241 struct wake_status **status) 242 { 243 spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status); 244 } 245 246 void mt_spm_idle_generic_init(void) 247 { 248 spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl); 249 } 250