1*ebb44440SRoger Lu /* 2*ebb44440SRoger Lu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*ebb44440SRoger Lu * 4*ebb44440SRoger Lu * SPDX-License-Identifier: BSD-3-Clause 5*ebb44440SRoger Lu */ 6*ebb44440SRoger Lu 7*ebb44440SRoger Lu #ifndef MT_SPM_CONSTRAINT_H 8*ebb44440SRoger Lu #define MT_SPM_CONSTRAINT_H 9*ebb44440SRoger Lu 10*ebb44440SRoger Lu #include <mt_lp_rm.h> 11*ebb44440SRoger Lu 12*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF (1U << 0) 13*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 (1U << 1) 14*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 (1U << 2) 15*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_VCORE_LP (1U << 3) 16*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN (1U << 4) 17*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF (1U << 5) 18*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND (1U << 6) 19*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_BBLPM (1U << 7) 20*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_XO_UFS (1U << 8) 21*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_GPS_STATE (1U << 9) 22*ebb44440SRoger Lu #define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE (1U << 10) 23*ebb44440SRoger Lu 24*ebb44440SRoger Lu #define MT_SPM_RC_INVALID 0x0 25*ebb44440SRoger Lu #define MT_SPM_RC_VALID_SW (1U << 0) 26*ebb44440SRoger Lu #define MT_SPM_RC_VALID_FW (1U << 1) 27*ebb44440SRoger Lu #define MT_SPM_RC_VALID_RESIDNECY (1U << 2) 28*ebb44440SRoger Lu #define MT_SPM_RC_VALID_COND_CHECK (1U << 3) 29*ebb44440SRoger Lu #define MT_SPM_RC_VALID_COND_LATCH (1U << 4) 30*ebb44440SRoger Lu #define MT_SPM_RC_VALID_UFS_H8 (1U << 5) 31*ebb44440SRoger Lu #define MT_SPM_RC_VALID_FLIGHTMODE (1U << 6) 32*ebb44440SRoger Lu #define MT_SPM_RC_VALID_XSOC_BBLPM (1U << 7) 33*ebb44440SRoger Lu #define MT_SPM_RC_VALID_TRACE_EVENT (1U << 8) 34*ebb44440SRoger Lu 35*ebb44440SRoger Lu #define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW) 36*ebb44440SRoger Lu 37*ebb44440SRoger Lu #define IS_MT_RM_RC_READY(status) \ 38*ebb44440SRoger Lu ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID) 39*ebb44440SRoger Lu 40*ebb44440SRoger Lu #define MT_SPM_RC_BBLPM_MODE \ 41*ebb44440SRoger Lu (MT_SPM_RC_VALID_UFS_H8 | \ 42*ebb44440SRoger Lu MT_SPM_RC_VALID_FLIGHTMODE | \ 43*ebb44440SRoger Lu MT_SPM_RC_VALID_XSOC_BBLPM) 44*ebb44440SRoger Lu 45*ebb44440SRoger Lu #define IS_MT_SPM_RC_BBLPM_MODE(st) \ 46*ebb44440SRoger Lu ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE) 47*ebb44440SRoger Lu 48*ebb44440SRoger Lu struct constraint_status { 49*ebb44440SRoger Lu uint16_t id; 50*ebb44440SRoger Lu uint16_t valid; 51*ebb44440SRoger Lu uint32_t cond_block; 52*ebb44440SRoger Lu uint32_t enter_cnt; 53*ebb44440SRoger Lu struct mt_spm_cond_tables *cond_res; 54*ebb44440SRoger Lu }; 55*ebb44440SRoger Lu 56*ebb44440SRoger Lu enum MT_SPM_RM_RC_TYPE { 57*ebb44440SRoger Lu MT_RM_CONSTRAINT_ID_BUS26M, 58*ebb44440SRoger Lu MT_RM_CONSTRAINT_ID_SYSPLL, 59*ebb44440SRoger Lu MT_RM_CONSTRAINT_ID_DRAM, 60*ebb44440SRoger Lu MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO, 61*ebb44440SRoger Lu MT_RM_CONSTRAINT_ID_ALL, 62*ebb44440SRoger Lu }; 63*ebb44440SRoger Lu #endif /* MT_SPM_CONSTRAINT_H */ 64