1 /* 2 * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_CONDIT_H 8 #define MT_SPM_CONDIT_H 9 10 #include <mt_lp_rm.h> 11 12 enum PLAT_SPM_COND { 13 PLAT_SPM_COND_MTCMOS1 = 0, 14 PLAT_SPM_COND_CG_INFRA_0, 15 PLAT_SPM_COND_CG_INFRA_1, 16 PLAT_SPM_COND_CG_INFRA_2, 17 PLAT_SPM_COND_CG_INFRA_3, 18 PLAT_SPM_COND_CG_INFRA_4, 19 PLAT_SPM_COND_CG_INFRA_5, 20 PLAT_SPM_COND_CG_MMSYS_0, 21 PLAT_SPM_COND_CG_MMSYS_1, 22 PLAT_SPM_COND_CG_MMSYS_2, 23 PLAT_SPM_COND_MAX, 24 }; 25 26 enum PLAT_SPM_COND_PLL { 27 PLAT_SPM_COND_PLL_UNIVPLL = 0, 28 PLAT_SPM_COND_PLL_MFGPLL, 29 PLAT_SPM_COND_PLL_MSDCPLL, 30 PLAT_SPM_COND_PLL_TVDPLL, 31 PLAT_SPM_COND_PLL_MMPLL, 32 PLAT_SPM_COND_PLL_MAX, 33 }; 34 35 #define PLL_BIT_MFGPLL (PLAT_SPM_COND_PLL_MFGPLL) 36 #define PLL_BIT_MMPLL (PLAT_SPM_COND_PLL_MMPLL) 37 #define PLL_BIT_UNIVPLL (PLAT_SPM_COND_PLL_UNIVPLL) 38 #define PLL_BIT_MSDCPLL (PLAT_SPM_COND_PLL_MSDCPLL) 39 #define PLL_BIT_TVDPLL (PLAT_SPM_COND_PLL_TVDPLL) 40 41 /* Definition about SPM_COND_CHECK_BLOCKED 42 * bit [00 ~ 15]: cg blocking index 43 * bit [16 ~ 29]: pll blocking index 44 * bit [30] : pll blocking information 45 * bit [31] : idle condition check fail 46 */ 47 #define SPM_COND_BLOCKED_CG_IDX U(0) 48 #define SPM_COND_BLOCKED_PLL_IDX U(16) 49 #define SPM_COND_CHECK_BLOCKED_PLL BIT(30) 50 #define SPM_COND_CHECK_FAIL BIT(31) 51 52 struct mt_spm_cond_tables { 53 char *name; 54 unsigned int table_cg[PLAT_SPM_COND_MAX]; 55 unsigned int table_pll; 56 void *priv; 57 }; 58 59 extern unsigned int mt_spm_cond_check(int state_id, 60 const struct mt_spm_cond_tables *src, 61 const struct mt_spm_cond_tables *dest, 62 struct mt_spm_cond_tables *res); 63 extern int mt_spm_cond_update(struct mt_resource_constraint **con, 64 int stateid, void *priv); 65 #endif /* MT_SPM_CONDIT_H */ 66