1 /* 2 * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <common/debug.h> 10 #include <lib/mmio.h> 11 12 #include <mt_spm_cond.h> 13 #include <mt_spm_conservation.h> 14 #include <mt_spm_constraint.h> 15 #include <plat_mtk_lpm.h> 16 #include <plat_pm.h> 17 #include <platform_def.h> 18 19 #define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs) 20 #define MT_LP_TZ_MM_REG(ofs) (MMSYS_BASE + ofs) 21 #define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs) 22 #define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEN_BASE + ofs) 23 #define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs) 24 25 #define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C) 26 #define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170) 27 #define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0094) 28 #define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0090) 29 #define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC) 30 #define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8) 31 #define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00D8) 32 #define INFRA_SW_CG5 MT_LP_TZ_INFRA_REG(0x00E8) 33 #define MMSYS_CG_CON0 MT_LP_TZ_MM_REG(0x100) 34 #define MMSYS_CG_CON1 MT_LP_TZ_MM_REG(0x110) 35 #define MMSYS_CG_CON2 MT_LP_TZ_MM_REG(0x1A0) 36 37 /*********************************************************** 38 * Check clkmux registers 39 ***********************************************************/ 40 #define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x20 + id * 0x10) 41 #define PDN_CHECK BIT(7) 42 #define CLK_CHECK BIT(31) 43 44 enum { 45 CLKMUX_DISP = 0, 46 CLKMUX_MDP = 1, 47 CLKMUX_IMG1 = 2, 48 CLKMUX_IMG2 = 3, 49 NF_CLKMUX, 50 }; 51 52 static bool is_clkmux_pdn(unsigned int clkmux_id) 53 { 54 unsigned int reg, val, idx; 55 56 if ((clkmux_id & CLK_CHECK) != 0U) { 57 clkmux_id = (clkmux_id & ~CLK_CHECK); 58 reg = clkmux_id / 4U; 59 val = mmio_read_32(CLK_CFG(reg)); 60 idx = clkmux_id % 4U; 61 val = (val >> (idx * 8U)) & PDN_CHECK; 62 return (val != 0U); 63 } 64 65 return false; 66 } 67 68 static struct mt_spm_cond_tables spm_cond_t; 69 70 struct idle_cond_info { 71 unsigned int subsys_mask; 72 uintptr_t addr; 73 bool bBitflip; 74 unsigned int clkmux_id; 75 }; 76 77 #define IDLE_CG(mask, addr, bitflip, clkmux) \ 78 {mask, (uintptr_t)addr, bitflip, clkmux} 79 80 static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = { 81 IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U), 82 IDLE_CG(0x00000200, INFRA_SW_CG0, true, 0U), 83 IDLE_CG(0x00000200, INFRA_SW_CG1, true, 0U), 84 IDLE_CG(0x00000200, INFRA_SW_CG2, true, 0U), 85 IDLE_CG(0x00000200, INFRA_SW_CG3, true, 0U), 86 IDLE_CG(0x00000200, INFRA_SW_CG4, true, 0U), 87 IDLE_CG(0x00000200, INFRA_SW_CG5, true, 0U), 88 IDLE_CG(0x00100000, MMSYS_CG_CON0, true, (CLK_CHECK | CLKMUX_DISP)), 89 IDLE_CG(0x00100000, MMSYS_CG_CON1, true, (CLK_CHECK | CLKMUX_DISP)), 90 IDLE_CG(0x00100000, MMSYS_CG_CON2, true, (CLK_CHECK | CLKMUX_DISP)), 91 }; 92 93 /*********************************************************** 94 * Check pll idle condition 95 ***********************************************************/ 96 #define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x268) 97 #define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x360) 98 #define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x308) 99 #define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x350) 100 #define PLL_TVDPLL MT_LP_TZ_APMIXEDSYS(0x380) 101 102 unsigned int mt_spm_cond_check(int state_id, 103 const struct mt_spm_cond_tables *src, 104 const struct mt_spm_cond_tables *dest, 105 struct mt_spm_cond_tables *res) 106 { 107 unsigned int blocked = 0U, i; 108 bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id); 109 110 if ((src == NULL) || (dest == NULL)) { 111 return SPM_COND_CHECK_FAIL; 112 } 113 114 for (i = 0U; i < PLAT_SPM_COND_MAX; i++) { 115 if (res != NULL) { 116 res->table_cg[i] = 117 (src->table_cg[i] & dest->table_cg[i]); 118 119 if (is_system_suspend && (res->table_cg[i] != 0U)) { 120 INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n", 121 dest->name, i, idle_cg_info[i].addr, 122 res->table_cg[i]); 123 } 124 125 if (res->table_cg[i] != 0U) { 126 blocked |= (1U << i); 127 } 128 } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) { 129 blocked |= (1U << i); 130 break; 131 } 132 } 133 134 if (res != NULL) { 135 res->table_pll = (src->table_pll & dest->table_pll); 136 137 if (res->table_pll != 0U) { 138 blocked |= 139 (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) | 140 SPM_COND_CHECK_BLOCKED_PLL; 141 } 142 } else if ((src->table_pll & dest->table_pll) != 0U) { 143 blocked |= SPM_COND_CHECK_BLOCKED_PLL; 144 } 145 146 if (is_system_suspend && (blocked != 0U)) { 147 INFO("suspend: %s total blocked = 0x%08x\n", 148 dest->name, blocked); 149 } 150 151 return blocked; 152 } 153 154 #define IS_MT_SPM_PWR_OFF(mask) \ 155 (((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \ 156 ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U)) 157 158 int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num, 159 int stateid, void *priv) 160 { 161 int res; 162 uint32_t i; 163 struct mt_resource_constraint *const *rc; 164 165 /* read all cg state */ 166 for (i = 0U; i < PLAT_SPM_COND_MAX; i++) { 167 spm_cond_t.table_cg[i] = 0U; 168 169 /* check mtcmos, if off set idle_value and clk to 0 disable */ 170 if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) { 171 continue; 172 } 173 174 /* check clkmux */ 175 if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) { 176 continue; 177 } 178 179 spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ? 180 ~mmio_read_32(idle_cg_info[i].addr) : 181 mmio_read_32(idle_cg_info[i].addr); 182 } 183 184 spm_cond_t.table_pll = 0U; 185 if ((mmio_read_32(PLL_MFGPLL) & 0x1) != 0U) { 186 spm_cond_t.table_pll |= PLL_BIT_MFGPLL; 187 } 188 189 if ((mmio_read_32(PLL_MMPLL) & 0x1) != 0U) { 190 spm_cond_t.table_pll |= PLL_BIT_MMPLL; 191 } 192 193 if ((mmio_read_32(PLL_UNIVPLL) & 0x1) != 0U) { 194 spm_cond_t.table_pll |= PLL_BIT_UNIVPLL; 195 } 196 197 if ((mmio_read_32(PLL_MSDCPLL) & 0x1) != 0U) { 198 spm_cond_t.table_pll |= PLL_BIT_MSDCPLL; 199 } 200 201 if ((mmio_read_32(PLL_TVDPLL) & 0x1) != 0U) { 202 spm_cond_t.table_pll |= PLL_BIT_TVDPLL; 203 } 204 205 spm_cond_t.priv = priv; 206 for (rc = con; *rc != NULL; rc++) { 207 if (((*rc)->update) == NULL) { 208 continue; 209 } 210 211 res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION, 212 (void const *)&spm_cond_t); 213 if (res != MT_RM_STATUS_OK) { 214 break; 215 } 216 } 217 218 return 0; 219 } 220