1*8709c939Selly.chiang /* 2*8709c939Selly.chiang * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*8709c939Selly.chiang * 4*8709c939Selly.chiang * SPDX-License-Identifier: BSD-3-Clause 5*8709c939Selly.chiang */ 6*8709c939Selly.chiang 7*8709c939Selly.chiang #ifndef MTK_PTP3_H 8*8709c939Selly.chiang #define MTK_PTP3_H 9*8709c939Selly.chiang 10*8709c939Selly.chiang #include <lib/mmio.h> 11*8709c939Selly.chiang #include <lib/utils_def.h> 12*8709c939Selly.chiang 13*8709c939Selly.chiang /************************************************ 14*8709c939Selly.chiang * BIT Operation and REG r/w 15*8709c939Selly.chiang ************************************************/ 16*8709c939Selly.chiang #define ptp3_read(addr) mmio_read_32((uintptr_t)addr) 17*8709c939Selly.chiang #define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val) 18*8709c939Selly.chiang 19*8709c939Selly.chiang /************************************************ 20*8709c939Selly.chiang * CPU info 21*8709c939Selly.chiang ************************************************/ 22*8709c939Selly.chiang #define NR_PTP3_CFG1_CPU U(8) 23*8709c939Selly.chiang #define PTP3_CFG1_CPU_START_ID U(0) 24*8709c939Selly.chiang #define PTP3_CFG1_MASK 0x00100000 25*8709c939Selly.chiang 26*8709c939Selly.chiang #define NR_PTP3_CFG2_CPU U(4) 27*8709c939Selly.chiang #define PTP3_CFG2_CPU_START_ID U(4) 28*8709c939Selly.chiang 29*8709c939Selly.chiang #define NR_PTP3_CFG3_CPU U(4) 30*8709c939Selly.chiang #define PTP3_CFG3_CPU_START_ID U(4) 31*8709c939Selly.chiang 32*8709c939Selly.chiang /************************************************ 33*8709c939Selly.chiang * config enum 34*8709c939Selly.chiang ************************************************/ 35*8709c939Selly.chiang enum PTP3_CFG { 36*8709c939Selly.chiang PTP3_CFG_ADDR, 37*8709c939Selly.chiang PTP3_CFG_VALUE, 38*8709c939Selly.chiang NR_PTP3_CFG, 39*8709c939Selly.chiang }; 40*8709c939Selly.chiang 41*8709c939Selly.chiang /************************************ 42*8709c939Selly.chiang * prototype 43*8709c939Selly.chiang ************************************/ 44*8709c939Selly.chiang /* init trigger for ptp3 feature */ 45*8709c939Selly.chiang extern void ptp3_init(unsigned int core); 46*8709c939Selly.chiang extern void ptp3_deinit(unsigned int core); 47*8709c939Selly.chiang 48*8709c939Selly.chiang #endif /* MTK_PTP3_H */ 49