1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <common/debug.h> 8 #include <lib/mmio.h> 9 #include <mtk_sip_svc.h> 10 #include <plat_dfd.h> 11 12 static bool dfd_enabled; 13 static uint64_t dfd_base_addr; 14 static uint64_t dfd_chain_length; 15 static uint64_t dfd_cache_dump; 16 17 static void dfd_setup(uint64_t base_addr, uint64_t chain_length, 18 uint64_t cache_dump) 19 { 20 /* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */ 21 /* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */ 22 sync_writel(DFD_INTERNAL_CTL, 0x5); 23 24 /* bit[13]: xreset_b_update_disable */ 25 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); 26 27 /* 28 * bit[10:3]: DFD trigger selection mask 29 * bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger) 30 * bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger) 31 * bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger) 32 * bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger) 33 * bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger) 34 */ 35 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 3); 36 37 /* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */ 38 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); 39 40 /* 41 * bit[0]: rg_rw_dfd_auto_power_on = 1 42 * bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us) 43 * bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us) 44 */ 45 mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); 46 47 /* longest scan chain length */ 48 mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); 49 50 /* bit[1:0]: rg_rw_dfd_shift_clock_ratio */ 51 mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); 52 53 /* rg_dfd_test_so_over_64 */ 54 mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); 55 56 /* DFD3.0 */ 57 mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_DIS_VAL); 58 mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL); 59 mmio_write_32(DFD_TEST_SI_2, DFD_TEST_SI_2_VAL); 60 mmio_write_32(DFD_TEST_SI_3, DFD_TEST_SI_3_VAL); 61 62 /* for iLDO feature */ 63 sync_writel(DFD_POWER_CTL, 0xF9); 64 65 /* set base address */ 66 mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); 67 68 /* 69 * disable sleep protect of DFD 70 * 10001220[8]: protect_en_reg[8] 71 * 10001a3c[2]: infra_mcu_pwr_ctl_mask[2] 72 */ 73 mmio_clrbits_32(DFD_O_PROTECT_EN_REG, 1 << 8); 74 mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 1 << 2); 75 76 /* clean DFD trigger status */ 77 sync_writel(DFD_CLEAN_STATUS, 0x1); 78 sync_writel(DFD_CLEAN_STATUS, 0x0); 79 80 /* DFD-3.0 */ 81 sync_writel(DFD_V30_CTL, 0x1); 82 83 /* setup global variables for suspend and resume */ 84 dfd_enabled = true; 85 dfd_base_addr = base_addr; 86 dfd_chain_length = chain_length; 87 dfd_cache_dump = cache_dump; 88 89 if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { 90 /* DFD3.5 */ 91 mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_EN_VAL); 92 sync_writel(DFD_V35_ENALBE, 0x1); 93 sync_writel(DFD_V35_TAP_NUMBER, 0xB); 94 sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); 95 sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); 96 97 if (cache_dump & DFD_PARITY_ERR_TRIGGER) { 98 sync_writel(DFD_HW_TRIGGER_MASK, 0xC); 99 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); 100 } 101 } 102 dsbsy(); 103 } 104 105 void dfd_resume(void) 106 { 107 if (dfd_enabled == true) { 108 dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); 109 } 110 } 111 112 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, 113 uint64_t arg2, uint64_t arg3) 114 { 115 uint64_t ret = 0L; 116 117 switch (arg0) { 118 case PLAT_MTK_DFD_SETUP_MAGIC: 119 dfd_setup(arg1, arg2, arg3); 120 break; 121 case PLAT_MTK_DFD_READ_MAGIC: 122 /* only allow to access DFD register base + 0x200 */ 123 if (arg1 <= 0x200) { 124 ret = mmio_read_32(MISC1_CFG_BASE + arg1); 125 } 126 break; 127 case PLAT_MTK_DFD_WRITE_MAGIC: 128 /* only allow to access DFD register base + 0x200 */ 129 if (arg1 <= 0x200) { 130 sync_writel(MISC1_CFG_BASE + arg1, arg2); 131 } 132 break; 133 default: 134 ret = MTK_SIP_E_INVALID_PARAM; 135 break; 136 } 137 138 return ret; 139 } 140