1*5183e637SRex-BC Chen /* 2*5183e637SRex-BC Chen * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*5183e637SRex-BC Chen * 4*5183e637SRex-BC Chen * SPDX-License-Identifier: BSD-3-Clause 5*5183e637SRex-BC Chen */ 6*5183e637SRex-BC Chen #include <arch_helpers.h> 7*5183e637SRex-BC Chen #include <common/debug.h> 8*5183e637SRex-BC Chen #include <lib/mmio.h> 9*5183e637SRex-BC Chen #include <mtk_sip_svc.h> 10*5183e637SRex-BC Chen #include <plat_dfd.h> 11*5183e637SRex-BC Chen 12*5183e637SRex-BC Chen static bool dfd_enabled; 13*5183e637SRex-BC Chen static uint64_t dfd_base_addr; 14*5183e637SRex-BC Chen static uint64_t dfd_chain_length; 15*5183e637SRex-BC Chen static uint64_t dfd_cache_dump; 16*5183e637SRex-BC Chen 17*5183e637SRex-BC Chen static void dfd_setup(uint64_t base_addr, uint64_t chain_length, 18*5183e637SRex-BC Chen uint64_t cache_dump) 19*5183e637SRex-BC Chen { 20*5183e637SRex-BC Chen /* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */ 21*5183e637SRex-BC Chen /* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */ 22*5183e637SRex-BC Chen sync_writel(DFD_INTERNAL_CTL, 0x5); 23*5183e637SRex-BC Chen 24*5183e637SRex-BC Chen /* bit[13]: xreset_b_update_disable */ 25*5183e637SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); 26*5183e637SRex-BC Chen 27*5183e637SRex-BC Chen /* 28*5183e637SRex-BC Chen * bit[10:3]: DFD trigger selection mask 29*5183e637SRex-BC Chen * bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger) 30*5183e637SRex-BC Chen * bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger) 31*5183e637SRex-BC Chen * bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger) 32*5183e637SRex-BC Chen * bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger) 33*5183e637SRex-BC Chen * bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger) 34*5183e637SRex-BC Chen */ 35*5183e637SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 3); 36*5183e637SRex-BC Chen 37*5183e637SRex-BC Chen /* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */ 38*5183e637SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); 39*5183e637SRex-BC Chen 40*5183e637SRex-BC Chen /* 41*5183e637SRex-BC Chen * bit[0]: rg_rw_dfd_auto_power_on = 1 42*5183e637SRex-BC Chen * bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us) 43*5183e637SRex-BC Chen * bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us) 44*5183e637SRex-BC Chen */ 45*5183e637SRex-BC Chen mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); 46*5183e637SRex-BC Chen 47*5183e637SRex-BC Chen /* longest scan chain length */ 48*5183e637SRex-BC Chen mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); 49*5183e637SRex-BC Chen 50*5183e637SRex-BC Chen /* bit[1:0]: rg_rw_dfd_shift_clock_ratio */ 51*5183e637SRex-BC Chen mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); 52*5183e637SRex-BC Chen 53*5183e637SRex-BC Chen /* rg_dfd_test_so_over_64 */ 54*5183e637SRex-BC Chen mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); 55*5183e637SRex-BC Chen 56*5183e637SRex-BC Chen /* DFD3.0 */ 57*5183e637SRex-BC Chen mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_DIS_VAL); 58*5183e637SRex-BC Chen mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL); 59*5183e637SRex-BC Chen mmio_write_32(DFD_TEST_SI_2, DFD_TEST_SI_2_VAL); 60*5183e637SRex-BC Chen mmio_write_32(DFD_TEST_SI_3, DFD_TEST_SI_3_VAL); 61*5183e637SRex-BC Chen 62*5183e637SRex-BC Chen /* for iLDO feature */ 63*5183e637SRex-BC Chen sync_writel(DFD_POWER_CTL, 0xF9); 64*5183e637SRex-BC Chen 65*5183e637SRex-BC Chen /* set base address */ 66*5183e637SRex-BC Chen mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); 67*5183e637SRex-BC Chen 68*5183e637SRex-BC Chen /* 69*5183e637SRex-BC Chen * disable sleep protect of DFD 70*5183e637SRex-BC Chen * 10001220[8]: protect_en_reg[8] 71*5183e637SRex-BC Chen * 10001a3c[2]: infra_mcu_pwr_ctl_mask[2] 72*5183e637SRex-BC Chen */ 73*5183e637SRex-BC Chen mmio_clrbits_32(DFD_O_PROTECT_EN_REG, 1 << 8); 74*5183e637SRex-BC Chen mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 1 << 2); 75*5183e637SRex-BC Chen 76*5183e637SRex-BC Chen /* clean DFD trigger status */ 77*5183e637SRex-BC Chen sync_writel(DFD_CLEAN_STATUS, 0x1); 78*5183e637SRex-BC Chen sync_writel(DFD_CLEAN_STATUS, 0x0); 79*5183e637SRex-BC Chen 80*5183e637SRex-BC Chen /* DFD-3.0 */ 81*5183e637SRex-BC Chen sync_writel(DFD_V30_CTL, 0x1); 82*5183e637SRex-BC Chen 83*5183e637SRex-BC Chen /* setup global variables for suspend and resume */ 84*5183e637SRex-BC Chen dfd_enabled = true; 85*5183e637SRex-BC Chen dfd_base_addr = base_addr; 86*5183e637SRex-BC Chen dfd_chain_length = chain_length; 87*5183e637SRex-BC Chen dfd_cache_dump = cache_dump; 88*5183e637SRex-BC Chen 89*5183e637SRex-BC Chen if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { 90*5183e637SRex-BC Chen /* DFD3.5 */ 91*5183e637SRex-BC Chen mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_EN_VAL); 92*5183e637SRex-BC Chen sync_writel(DFD_V35_ENALBE, 0x1); 93*5183e637SRex-BC Chen sync_writel(DFD_V35_TAP_NUMBER, 0xB); 94*5183e637SRex-BC Chen sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); 95*5183e637SRex-BC Chen sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); 96*5183e637SRex-BC Chen 97*5183e637SRex-BC Chen if (cache_dump & DFD_PARITY_ERR_TRIGGER) { 98*5183e637SRex-BC Chen sync_writel(DFD_HW_TRIGGER_MASK, 0xC); 99*5183e637SRex-BC Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); 100*5183e637SRex-BC Chen } 101*5183e637SRex-BC Chen } 102*5183e637SRex-BC Chen dsbsy(); 103*5183e637SRex-BC Chen } 104*5183e637SRex-BC Chen 105*5183e637SRex-BC Chen void dfd_resume(void) 106*5183e637SRex-BC Chen { 107*5183e637SRex-BC Chen if (dfd_enabled == true) { 108*5183e637SRex-BC Chen dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); 109*5183e637SRex-BC Chen } 110*5183e637SRex-BC Chen } 111*5183e637SRex-BC Chen 112*5183e637SRex-BC Chen uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, 113*5183e637SRex-BC Chen uint64_t arg2, uint64_t arg3) 114*5183e637SRex-BC Chen { 115*5183e637SRex-BC Chen uint64_t ret = 0L; 116*5183e637SRex-BC Chen 117*5183e637SRex-BC Chen switch (arg0) { 118*5183e637SRex-BC Chen case PLAT_MTK_DFD_SETUP_MAGIC: 119*5183e637SRex-BC Chen dfd_setup(arg1, arg2, arg3); 120*5183e637SRex-BC Chen break; 121*5183e637SRex-BC Chen case PLAT_MTK_DFD_READ_MAGIC: 122*5183e637SRex-BC Chen /* only allow to access DFD register base + 0x200 */ 123*5183e637SRex-BC Chen if (arg1 <= 0x200) { 124*5183e637SRex-BC Chen ret = mmio_read_32(MISC1_CFG_BASE + arg1); 125*5183e637SRex-BC Chen } 126*5183e637SRex-BC Chen break; 127*5183e637SRex-BC Chen case PLAT_MTK_DFD_WRITE_MAGIC: 128*5183e637SRex-BC Chen /* only allow to access DFD register base + 0x200 */ 129*5183e637SRex-BC Chen if (arg1 <= 0x200) { 130*5183e637SRex-BC Chen sync_writel(MISC1_CFG_BASE + arg1, arg2); 131*5183e637SRex-BC Chen } 132*5183e637SRex-BC Chen break; 133*5183e637SRex-BC Chen default: 134*5183e637SRex-BC Chen ret = MTK_SIP_E_INVALID_PARAM; 135*5183e637SRex-BC Chen break; 136*5183e637SRex-BC Chen } 137*5183e637SRex-BC Chen 138*5183e637SRex-BC Chen return ret; 139*5183e637SRex-BC Chen } 140