xref: /rk3399_ARM-atf/plat/mediatek/mt8192/bl31_plat_setup.c (revision 95cc8894886b92f4749999a25297bc5942a97d7b)
1f85f37d4SNina Wu /*
2f85f37d4SNina Wu  * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3f85f37d4SNina Wu  *
4f85f37d4SNina Wu  * SPDX-License-Identifier: BSD-3-Clause
5f85f37d4SNina Wu  */
6f85f37d4SNina Wu 
7f85f37d4SNina Wu /* System Includes */
8f85f37d4SNina Wu #include <assert.h>
9f85f37d4SNina Wu 
10f85f37d4SNina Wu /* Project Includes */
11f85f37d4SNina Wu #include <common/bl_common.h>
12f85f37d4SNina Wu #include <common/debug.h>
13f85f37d4SNina Wu #include <common/desc_image_load.h>
14*95cc8894SNina Wu #include <drivers/generic_delay_timer.h>
15f85f37d4SNina Wu #include <drivers/ti/uart/uart_16550.h>
16f85f37d4SNina Wu #include <lib/coreboot.h>
17f85f37d4SNina Wu 
18f85f37d4SNina Wu /* Platform Includes */
19054af8f2SPo Xu #include <gpio/mtgpio.h>
2074f72b13SGreta Zhang #include <mt_gic_v3.h>
21f3fbacaaSDehui Sun #include <mt_timer.h>
22f85f37d4SNina Wu #include <plat_params.h>
23f85f37d4SNina Wu #include <plat_private.h>
24f85f37d4SNina Wu 
25f85f37d4SNina Wu static entry_point_info_t bl32_ep_info;
26f85f37d4SNina Wu static entry_point_info_t bl33_ep_info;
27f85f37d4SNina Wu 
28f85f37d4SNina Wu /*******************************************************************************
29f85f37d4SNina Wu  * Return a pointer to the 'entry_point_info' structure of the next image for
30f85f37d4SNina Wu  * the security state specified. BL33 corresponds to the non-secure image type
31f85f37d4SNina Wu  * while BL32 corresponds to the secure image type. A NULL pointer is returned
32f85f37d4SNina Wu  * if the image does not exist.
33f85f37d4SNina Wu  ******************************************************************************/
34f85f37d4SNina Wu entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
35f85f37d4SNina Wu {
36f85f37d4SNina Wu 	entry_point_info_t *next_image_info;
37f85f37d4SNina Wu 
38f85f37d4SNina Wu 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
39f85f37d4SNina Wu 	assert(next_image_info->h.type == PARAM_EP);
40f85f37d4SNina Wu 
41f85f37d4SNina Wu 	/* None of the images on this platform can have 0x0 as the entrypoint */
42f85f37d4SNina Wu 	if (next_image_info->pc) {
43f85f37d4SNina Wu 		return next_image_info;
44f85f37d4SNina Wu 	} else {
45f85f37d4SNina Wu 		return NULL;
46f85f37d4SNina Wu 	}
47f85f37d4SNina Wu }
48f85f37d4SNina Wu 
49f85f37d4SNina Wu /*******************************************************************************
50f85f37d4SNina Wu  * Perform any BL31 early platform setup. Here is an opportunity to copy
51f85f37d4SNina Wu  * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
52f85f37d4SNina Wu  * are lost (potentially). This needs to be done before the MMU is initialized
53f85f37d4SNina Wu  * so that the memory layout can be used while creating page tables.
54f85f37d4SNina Wu  * BL2 has flushed this information to memory, so we are guaranteed to pick up
55f85f37d4SNina Wu  * good data.
56f85f37d4SNina Wu  ******************************************************************************/
57f85f37d4SNina Wu void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
58f85f37d4SNina Wu 				u_register_t arg2, u_register_t arg3)
59f85f37d4SNina Wu {
60f85f37d4SNina Wu 	static console_t console;
61f85f37d4SNina Wu 
62f85f37d4SNina Wu 	params_early_setup(arg1);
63f85f37d4SNina Wu 
64f85f37d4SNina Wu #if COREBOOT
65f85f37d4SNina Wu 	if (coreboot_serial.type) {
66f85f37d4SNina Wu 		console_16550_register(coreboot_serial.baseaddr,
67f85f37d4SNina Wu 				       coreboot_serial.input_hertz,
68f85f37d4SNina Wu 				       coreboot_serial.baud,
69f85f37d4SNina Wu 				       &console);
70f85f37d4SNina Wu 	}
71f85f37d4SNina Wu #else
72f85f37d4SNina Wu 	console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
73f85f37d4SNina Wu #endif
74f85f37d4SNina Wu 
75f85f37d4SNina Wu 	NOTICE("MT8192 bl31_setup\n");
76f85f37d4SNina Wu 
77f85f37d4SNina Wu 	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
78f85f37d4SNina Wu }
79f85f37d4SNina Wu 
80f85f37d4SNina Wu 
81f85f37d4SNina Wu /*******************************************************************************
82f85f37d4SNina Wu  * Perform any BL31 platform setup code
83f85f37d4SNina Wu  ******************************************************************************/
84f85f37d4SNina Wu void bl31_platform_setup(void)
85f85f37d4SNina Wu {
8674f72b13SGreta Zhang 	/* Initialize the GIC driver, CPU and distributor interfaces */
8774f72b13SGreta Zhang 	mt_gic_driver_init();
8874f72b13SGreta Zhang 	mt_gic_init();
89f3fbacaaSDehui Sun 
90054af8f2SPo Xu 	plat_mt8192_gpio_init();
91f3fbacaaSDehui Sun 	mt_systimer_init();
92*95cc8894SNina Wu 	generic_delay_timer_init();
93f85f37d4SNina Wu }
94f85f37d4SNina Wu 
95f85f37d4SNina Wu /*******************************************************************************
96f85f37d4SNina Wu  * Perform the very early platform specific architectural setup here. At the
97f85f37d4SNina Wu  * moment this is only intializes the mmu in a quick and dirty way.
98f85f37d4SNina Wu  ******************************************************************************/
99f85f37d4SNina Wu void bl31_plat_arch_setup(void)
100f85f37d4SNina Wu {
101f85f37d4SNina Wu 	plat_configure_mmu_el3(BL31_START,
102f85f37d4SNina Wu 			       BL31_END - BL31_START,
103f85f37d4SNina Wu 			       BL_CODE_BASE,
104f85f37d4SNina Wu 			       BL_CODE_END);
105f85f37d4SNina Wu }
106