xref: /rk3399_ARM-atf/plat/mediatek/mt8192/bl31_plat_setup.c (revision 4bd8c929b4bc6e1731c2892b38d4a8c43e8e89dc)
1f85f37d4SNina Wu /*
2f85f37d4SNina Wu  * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3f85f37d4SNina Wu  *
4f85f37d4SNina Wu  * SPDX-License-Identifier: BSD-3-Clause
5f85f37d4SNina Wu  */
6f85f37d4SNina Wu 
7f85f37d4SNina Wu /* System Includes */
8f85f37d4SNina Wu #include <assert.h>
9f85f37d4SNina Wu 
10f85f37d4SNina Wu /* Project Includes */
11f85f37d4SNina Wu #include <common/bl_common.h>
12f85f37d4SNina Wu #include <common/debug.h>
13f85f37d4SNina Wu #include <common/desc_image_load.h>
1495cc8894SNina Wu #include <drivers/generic_delay_timer.h>
15f85f37d4SNina Wu #include <drivers/ti/uart/uart_16550.h>
16f85f37d4SNina Wu #include <lib/coreboot.h>
17f85f37d4SNina Wu 
18f85f37d4SNina Wu /* Platform Includes */
196b822d49SNina Wu #include <devapc/devapc.h>
2042f2fa82SXi Chen #include <emi_mpu/emi_mpu.h>
21054af8f2SPo Xu #include <gpio/mtgpio.h>
2274f72b13SGreta Zhang #include <mt_gic_v3.h>
23ebb44440SRoger Lu #include <mt_spm.h>
24f3fbacaaSDehui Sun #include <mt_timer.h>
2543d7bbccSNina Wu #include <mtk_dcm.h>
26f85f37d4SNina Wu #include <plat_params.h>
27f85f37d4SNina Wu #include <plat_private.h>
28f85f37d4SNina Wu 
29f85f37d4SNina Wu static entry_point_info_t bl32_ep_info;
30f85f37d4SNina Wu static entry_point_info_t bl33_ep_info;
31f85f37d4SNina Wu 
32f85f37d4SNina Wu /*******************************************************************************
33f85f37d4SNina Wu  * Return a pointer to the 'entry_point_info' structure of the next image for
34f85f37d4SNina Wu  * the security state specified. BL33 corresponds to the non-secure image type
35f85f37d4SNina Wu  * while BL32 corresponds to the secure image type. A NULL pointer is returned
36f85f37d4SNina Wu  * if the image does not exist.
37f85f37d4SNina Wu  ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)38f85f37d4SNina Wu entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
39f85f37d4SNina Wu {
40f85f37d4SNina Wu 	entry_point_info_t *next_image_info;
41f85f37d4SNina Wu 
42f85f37d4SNina Wu 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
43f85f37d4SNina Wu 	assert(next_image_info->h.type == PARAM_EP);
44f85f37d4SNina Wu 
45f85f37d4SNina Wu 	/* None of the images on this platform can have 0x0 as the entrypoint */
46f85f37d4SNina Wu 	if (next_image_info->pc) {
47f85f37d4SNina Wu 		return next_image_info;
48f85f37d4SNina Wu 	} else {
49f85f37d4SNina Wu 		return NULL;
50f85f37d4SNina Wu 	}
51f85f37d4SNina Wu }
52f85f37d4SNina Wu 
53f85f37d4SNina Wu /*******************************************************************************
54f85f37d4SNina Wu  * Perform any BL31 early platform setup. Here is an opportunity to copy
55f85f37d4SNina Wu  * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
56f85f37d4SNina Wu  * are lost (potentially). This needs to be done before the MMU is initialized
57f85f37d4SNina Wu  * so that the memory layout can be used while creating page tables.
58f85f37d4SNina Wu  * BL2 has flushed this information to memory, so we are guaranteed to pick up
59f85f37d4SNina Wu  * good data.
60f85f37d4SNina Wu  ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)61f85f37d4SNina Wu void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
62f85f37d4SNina Wu 				u_register_t arg2, u_register_t arg3)
63f85f37d4SNina Wu {
64f85f37d4SNina Wu 	static console_t console;
65f85f37d4SNina Wu 
66f85f37d4SNina Wu 	params_early_setup(arg1);
67f85f37d4SNina Wu 
68f85f37d4SNina Wu #if COREBOOT
69f85f37d4SNina Wu 	if (coreboot_serial.type) {
70f85f37d4SNina Wu 		console_16550_register(coreboot_serial.baseaddr,
71f85f37d4SNina Wu 				       coreboot_serial.input_hertz,
72f85f37d4SNina Wu 				       coreboot_serial.baud,
73f85f37d4SNina Wu 				       &console);
74f85f37d4SNina Wu 	}
75f85f37d4SNina Wu #else
76f85f37d4SNina Wu 	console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
77f85f37d4SNina Wu #endif
78f85f37d4SNina Wu 
79f85f37d4SNina Wu 	NOTICE("MT8192 bl31_setup\n");
80f85f37d4SNina Wu 
81f85f37d4SNina Wu 	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
82f85f37d4SNina Wu }
83f85f37d4SNina Wu 
84f85f37d4SNina Wu 
85f85f37d4SNina Wu /*******************************************************************************
86f85f37d4SNina Wu  * Perform any BL31 platform setup code
87f85f37d4SNina Wu  ******************************************************************************/
bl31_platform_setup(void)88f85f37d4SNina Wu void bl31_platform_setup(void)
89f85f37d4SNina Wu {
9043d7bbccSNina Wu 	/* Set dcm on */
9143d7bbccSNina Wu 	if (!dcm_set_default()) {
9243d7bbccSNina Wu 		ERROR("Failed to set default dcm on!!\n");
9343d7bbccSNina Wu 	}
9443d7bbccSNina Wu 
9542f2fa82SXi Chen 	/* MPU Init */
9642f2fa82SXi Chen 	emi_mpu_init();
9742f2fa82SXi Chen 
986b822d49SNina Wu 	/* DAPC Init */
996b822d49SNina Wu 	devapc_init();
1006b822d49SNina Wu 
10174f72b13SGreta Zhang 	/* Initialize the GIC driver, CPU and distributor interfaces */
10274f72b13SGreta Zhang 	mt_gic_driver_init();
10374f72b13SGreta Zhang 	mt_gic_init();
104f3fbacaaSDehui Sun 
105aebd4dc8Smtk20895 	mt_gpio_init();
106f3fbacaaSDehui Sun 	mt_systimer_init();
10795cc8894SNina Wu 	generic_delay_timer_init();
108ebb44440SRoger Lu 	spm_boot_init();
109f85f37d4SNina Wu }
110f85f37d4SNina Wu 
111f85f37d4SNina Wu /*******************************************************************************
112f85f37d4SNina Wu  * Perform the very early platform specific architectural setup here. At the
113*1b491eeaSElyes Haouas  * moment this is only initializes the mmu in a quick and dirty way.
114f85f37d4SNina Wu  ******************************************************************************/
bl31_plat_arch_setup(void)115f85f37d4SNina Wu void bl31_plat_arch_setup(void)
116f85f37d4SNina Wu {
117f85f37d4SNina Wu 	plat_configure_mmu_el3(BL31_START,
118f85f37d4SNina Wu 			       BL31_END - BL31_START,
119f85f37d4SNina Wu 			       BL_CODE_BASE,
120f85f37d4SNina Wu 			       BL_CODE_END);
121f85f37d4SNina Wu }
122