1f85f37d4SNina Wu /* 2f85f37d4SNina Wu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3f85f37d4SNina Wu * 4f85f37d4SNina Wu * SPDX-License-Identifier: BSD-3-Clause 5f85f37d4SNina Wu */ 6f85f37d4SNina Wu 7f85f37d4SNina Wu /* Project Includes */ 8f85f37d4SNina Wu #include <lib/xlat_tables/xlat_tables_v2.h> 9f85f37d4SNina Wu 10f85f37d4SNina Wu /* Platform Includes */ 11f85f37d4SNina Wu #include <platform_def.h> 12f85f37d4SNina Wu 13f85f37d4SNina Wu /* Table of regions to map using the MMU. */ 14f85f37d4SNina Wu const mmap_region_t plat_mmap[] = { 15f85f37d4SNina Wu /* for TF text, RO, RW */ 16f85f37d4SNina Wu MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, 17f85f37d4SNina Wu MT_DEVICE | MT_RW | MT_SECURE), 18f85f37d4SNina Wu MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, 19f85f37d4SNina Wu MT_DEVICE | MT_RW | MT_SECURE), 20f85f37d4SNina Wu MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE, 21f85f37d4SNina Wu MT_DEVICE | MT_RW | MT_SECURE), 22*df60025fSRoger Lu MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE, 23*df60025fSRoger Lu MT_DEVICE | MT_RW | MT_SECURE), 24f85f37d4SNina Wu { 0 } 25f85f37d4SNina Wu }; 26f85f37d4SNina Wu 27f85f37d4SNina Wu /******************************************************************************* 28f85f37d4SNina Wu * Macro generating the code for the function setting up the pagetables as per 29f85f37d4SNina Wu * the platform memory map & initialize the mmu, for the given exception level 30f85f37d4SNina Wu ******************************************************************************/ 31f85f37d4SNina Wu void plat_configure_mmu_el3(uintptr_t total_base, 32f85f37d4SNina Wu uintptr_t total_size, 33f85f37d4SNina Wu uintptr_t ro_start, 34f85f37d4SNina Wu uintptr_t ro_limit) 35f85f37d4SNina Wu { 36f85f37d4SNina Wu mmap_add_region(total_base, total_base, total_size, 37f85f37d4SNina Wu MT_RW_DATA | MT_SECURE); 38f85f37d4SNina Wu mmap_add_region(ro_start, ro_start, ro_limit - ro_start, 39f85f37d4SNina Wu MT_CODE | MT_SECURE); 40f85f37d4SNina Wu mmap_add(plat_mmap); 41f85f37d4SNina Wu init_xlat_tables(); 42f85f37d4SNina Wu enable_mmu_el3(0); 43f85f37d4SNina Wu } 44f85f37d4SNina Wu 45f85f37d4SNina Wu unsigned int plat_get_syscnt_freq2(void) 46f85f37d4SNina Wu { 47f85f37d4SNina Wu return SYS_COUNTER_FREQ_IN_TICKS; 48f85f37d4SNina Wu } 49