1f85f37d4SNina Wu /*
2f85f37d4SNina Wu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3f85f37d4SNina Wu *
4f85f37d4SNina Wu * SPDX-License-Identifier: BSD-3-Clause
5f85f37d4SNina Wu */
6f85f37d4SNina Wu
7f85f37d4SNina Wu /* Project Includes */
8f85f37d4SNina Wu #include <lib/xlat_tables/xlat_tables_v2.h>
9f85f37d4SNina Wu
10f85f37d4SNina Wu /* Platform Includes */
11f85f37d4SNina Wu #include <platform_def.h>
12f85f37d4SNina Wu
13f85f37d4SNina Wu /* Table of regions to map using the MMU. */
14f85f37d4SNina Wu const mmap_region_t plat_mmap[] = {
15f85f37d4SNina Wu /* for TF text, RO, RW */
16f85f37d4SNina Wu MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
17f85f37d4SNina Wu MT_DEVICE | MT_RW | MT_SECURE),
18f85f37d4SNina Wu MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
19f85f37d4SNina Wu MT_DEVICE | MT_RW | MT_SECURE),
20f85f37d4SNina Wu MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
21f85f37d4SNina Wu MT_DEVICE | MT_RW | MT_SECURE),
22df60025fSRoger Lu MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
23df60025fSRoger Lu MT_DEVICE | MT_RW | MT_SECURE),
24*2671f318SFlora Fu MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
25*2671f318SFlora Fu MT_DEVICE | MT_RW | MT_SECURE),
26*2671f318SFlora Fu MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE,
27*2671f318SFlora Fu MT_DEVICE | MT_RW | MT_SECURE),
28*2671f318SFlora Fu MAP_REGION_FLAT(APUSYS_APC_AO_WRAPPER_BASE, APUSYS_APC_AO_WRAPPER_SIZE,
29*2671f318SFlora Fu MT_DEVICE | MT_RW | MT_SECURE),
30*2671f318SFlora Fu MAP_REGION_FLAT(APUSYS_NOC_DAPC_AO_BASE, APUSYS_NOC_DAPC_AO_SIZE,
31*2671f318SFlora Fu MT_DEVICE | MT_RW | MT_SECURE),
32f85f37d4SNina Wu { 0 }
33f85f37d4SNina Wu };
34f85f37d4SNina Wu
35f85f37d4SNina Wu /*******************************************************************************
36f85f37d4SNina Wu * Macro generating the code for the function setting up the pagetables as per
37f85f37d4SNina Wu * the platform memory map & initialize the mmu, for the given exception level
38f85f37d4SNina Wu ******************************************************************************/
plat_configure_mmu_el3(uintptr_t total_base,uintptr_t total_size,uintptr_t ro_start,uintptr_t ro_limit)39f85f37d4SNina Wu void plat_configure_mmu_el3(uintptr_t total_base,
40f85f37d4SNina Wu uintptr_t total_size,
41f85f37d4SNina Wu uintptr_t ro_start,
42f85f37d4SNina Wu uintptr_t ro_limit)
43f85f37d4SNina Wu {
44f85f37d4SNina Wu mmap_add_region(total_base, total_base, total_size,
45f85f37d4SNina Wu MT_RW_DATA | MT_SECURE);
46f85f37d4SNina Wu mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
47f85f37d4SNina Wu MT_CODE | MT_SECURE);
48f85f37d4SNina Wu mmap_add(plat_mmap);
49f85f37d4SNina Wu init_xlat_tables();
50f85f37d4SNina Wu enable_mmu_el3(0);
51f85f37d4SNina Wu }
52f85f37d4SNina Wu
plat_get_syscnt_freq2(void)53f85f37d4SNina Wu unsigned int plat_get_syscnt_freq2(void)
54f85f37d4SNina Wu {
55f85f37d4SNina Wu return SYS_COUNTER_FREQ_IN_TICKS;
56f85f37d4SNina Wu }
57