1*f85f37d4SNina Wu/* 2*f85f37d4SNina Wu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*f85f37d4SNina Wu * 4*f85f37d4SNina Wu * SPDX-License-Identifier: BSD-3-Clause 5*f85f37d4SNina Wu */ 6*f85f37d4SNina Wu 7*f85f37d4SNina Wu#include <arch.h> 8*f85f37d4SNina Wu#include <asm_macros.S> 9*f85f37d4SNina Wu#include <platform_def.h> 10*f85f37d4SNina Wu 11*f85f37d4SNina Wu .globl plat_is_my_cpu_primary 12*f85f37d4SNina Wu .globl plat_my_core_pos 13*f85f37d4SNina Wu .globl plat_mediatek_calc_core_pos 14*f85f37d4SNina Wu 15*f85f37d4SNina Wufunc plat_is_my_cpu_primary 16*f85f37d4SNina Wu mrs x0, mpidr_el1 17*f85f37d4SNina Wu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 18*f85f37d4SNina Wu cmp x0, #PLAT_PRIMARY_CPU 19*f85f37d4SNina Wu cset x0, eq 20*f85f37d4SNina Wu ret 21*f85f37d4SNina Wuendfunc plat_is_my_cpu_primary 22*f85f37d4SNina Wu 23*f85f37d4SNina Wu /* ----------------------------------------------------- 24*f85f37d4SNina Wu * unsigned int plat_my_core_pos(void) 25*f85f37d4SNina Wu * This function uses the plat_mediatek_calc_core_pos() 26*f85f37d4SNina Wu * definition to get the index of the calling CPU. 27*f85f37d4SNina Wu * ----------------------------------------------------- 28*f85f37d4SNina Wu */ 29*f85f37d4SNina Wufunc plat_my_core_pos 30*f85f37d4SNina Wu mrs x0, mpidr_el1 31*f85f37d4SNina Wu b plat_mediatek_calc_core_pos 32*f85f37d4SNina Wuendfunc plat_my_core_pos 33*f85f37d4SNina Wu 34*f85f37d4SNina Wu /* ----------------------------------------------------- 35*f85f37d4SNina Wu * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr); 36*f85f37d4SNina Wu * 37*f85f37d4SNina Wu * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and 38*f85f37d4SNina Wu * AFF0 is thread id. There is only one cluster in ARMv8.2 39*f85f37d4SNina Wu * and one thread in current implementation. 40*f85f37d4SNina Wu * 41*f85f37d4SNina Wu * With this function: CorePos = CoreID (AFF1) 42*f85f37d4SNina Wu * we do it with x0 = (x0 >> 8) & 0xff 43*f85f37d4SNina Wu * ----------------------------------------------------- 44*f85f37d4SNina Wu */ 45*f85f37d4SNina Wufunc plat_mediatek_calc_core_pos 46*f85f37d4SNina Wu mov x1, #MPIDR_AFFLVL_MASK 47*f85f37d4SNina Wu and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT 48*f85f37d4SNina Wu ret 49*f85f37d4SNina Wuendfunc plat_mediatek_calc_core_pos 50