1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch_def.h> 11 12 #define PLAT_PRIMARY_CPU (0x0) 13 14 #define MT_GIC_BASE (0x0C000000) 15 #define MCUCFG_BASE (0x0C530000) 16 #define MCUCFG_REG_SIZE (0x10000) 17 #define IO_PHYS (0x10000000) 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21 #define MTK_DEV_RNG0_SIZE (0x600000) 22 #define MTK_DEV_RNG1_BASE (IO_PHYS) 23 #define MTK_DEV_RNG1_SIZE (0x10000000) 24 25 #define TOPCKGEN_BASE (IO_PHYS) 26 27 /******************************************************************************* 28 * UART related constants 29 ******************************************************************************/ 30 #define UART0_BASE (IO_PHYS + 0x01002000) 31 #define UART_BAUDRATE (115200) 32 33 /******************************************************************************* 34 * System counter frequency related constants 35 ******************************************************************************/ 36 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 37 #define SYS_COUNTER_FREQ_IN_MHZ (13) 38 39 /******************************************************************************* 40 * Platform binary types for linking 41 ******************************************************************************/ 42 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 43 #define PLATFORM_LINKER_ARCH aarch64 44 45 /******************************************************************************* 46 * Generic platform constants 47 ******************************************************************************/ 48 #define PLATFORM_STACK_SIZE (0x800) 49 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 50 #define SOC_CHIP_ID U(0x8189) 51 52 /******************************************************************************* 53 * Platform memory map related constants 54 ******************************************************************************/ 55 #define TZRAM_BASE (0x54600000) 56 #define TZRAM_SIZE (0x00200000) 57 58 /******************************************************************************* 59 * BL31 specific defines. 60 ******************************************************************************/ 61 /* 62 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 63 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 64 * little space for growth. 65 */ 66 #define BL31_BASE (TZRAM_BASE + 0x1000) 67 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 68 69 /******************************************************************************* 70 * Platform specific page table and MMU setup constants 71 ******************************************************************************/ 72 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 73 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 74 #define MAX_XLAT_TABLES (16) 75 #define MAX_MMAP_REGIONS (16) 76 77 /******************************************************************************* 78 * SYSTIMER related definitions 79 ******************************************************************************/ 80 #define SYSTIMER_BASE (IO_PHYS + 0x0CC10000) 81 82 #endif /* PLATFORM_DEF_H */ 83