xref: /rk3399_ARM-atf/plat/mediatek/mt8188/plat_config.mk (revision 45711e4e1614fbed75ea645777cc2bb11d4be96f)
1de310e1eSRex-BC Chen#
2de310e1eSRex-BC Chen# Copyright (c) 2022, MediaTek Inc. All rights reserved.
3de310e1eSRex-BC Chen#
4de310e1eSRex-BC Chen# SPDX-License-Identifier: BSD-3-Clause
5de310e1eSRex-BC Chen#
6de310e1eSRex-BC Chen
7de310e1eSRex-BC Chen# Separate text code and read only data
8de310e1eSRex-BC ChenSEPARATE_CODE_AND_RODATA := 1
9de310e1eSRex-BC Chen# ARMv8.2 and above need enable HW assist coherence
10de310e1eSRex-BC ChenHW_ASSISTED_COHERENCY := 1
11de310e1eSRex-BC Chen# No need coherency memory because of HW assistency
12de310e1eSRex-BC ChenUSE_COHERENT_MEM := 0
13de310e1eSRex-BC Chen# GIC600
14de310e1eSRex-BC ChenGICV3_SUPPORT_GIC600 := 1
15de310e1eSRex-BC Chen#
16de310e1eSRex-BC Chen# MTK options
17de310e1eSRex-BC Chen#
18de310e1eSRex-BC ChenPLAT_EXTRA_RODATA_INCLUDES := 1
19e9310c34SHui LiuUSE_PMIC_WRAP_INIT_V2 := 1
20af5d8e07SSong FanUSE_RTC_MT6359P := 1
21de310e1eSRex-BC Chen
22de310e1eSRex-BC Chen# Configs for A78 and A55
23de310e1eSRex-BC ChenCTX_INCLUDE_AARCH32_REGS := 0
24de310e1eSRex-BC ChenERRATA_A55_1530923 := 1
25de310e1eSRex-BC ChenERRATA_A55_1221012 := 1
26de310e1eSRex-BC ChenERRATA_A78_1688305 := 1
27de310e1eSRex-BC ChenERRATA_A78_1941498 := 1
28de310e1eSRex-BC ChenERRATA_A78_1951500 := 1
29de310e1eSRex-BC ChenERRATA_A78_1821534 := 1
30de310e1eSRex-BC ChenERRATA_A78_2132060 := 1
31de310e1eSRex-BC ChenERRATA_A78_2242635 := 1
32abb995abSBo-Chen ChenERRATA_A78_2376745 := 1
33abb995abSBo-Chen ChenERRATA_A78_2395406 := 1
34de310e1eSRex-BC Chen
35*45711e4eSEdward-JW YangCONFIG_ARCH_ARM_V8_2 := y
36de310e1eSRex-BC ChenMACH_MT8188 := 1
37de310e1eSRex-BC Chen$(eval $(call add_define,MACH_MT8188))
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