1 /* 2 * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch_def.h> 11 12 #define PLAT_PRIMARY_CPU (0x0) 13 14 #define MT_GIC_BASE (0x0C000000) 15 #define MCUCFG_BASE (0x0C530000) 16 #define MCUCFG_REG_SIZE (0x10000) 17 #define IO_PHYS (0x10000000) 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21 #define MTK_DEV_RNG0_SIZE (0x600000) 22 #define MTK_DEV_RNG1_BASE (IO_PHYS) 23 #define MTK_DEV_RNG1_SIZE (0x10000000) 24 25 #define TOPCKGEN_BASE (IO_PHYS) 26 27 /******************************************************************************* 28 * AUDIO related constants 29 ******************************************************************************/ 30 #define AUDIO_BASE (IO_PHYS + 0x00b10000) 31 32 /******************************************************************************* 33 * SPM related constants 34 ******************************************************************************/ 35 #define SPM_BASE (IO_PHYS + 0x00006000) 36 37 /******************************************************************************* 38 * GPIO related constants 39 ******************************************************************************/ 40 #define GPIO_BASE (IO_PHYS + 0x00005000) 41 #define RGU_BASE (IO_PHYS + 0x00007000) 42 #define DRM_BASE (IO_PHYS + 0x0000D000) 43 #define IOCFG_RM_BASE (IO_PHYS + 0x01C00000) 44 #define IOCFG_LT_BASE (IO_PHYS + 0x01E10000) 45 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 46 #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) 47 48 /******************************************************************************* 49 * UART related constants 50 ******************************************************************************/ 51 #define UART0_BASE (IO_PHYS + 0x01002000) 52 #define UART_BAUDRATE (115200) 53 54 /******************************************************************************* 55 * PMIC related constants 56 ******************************************************************************/ 57 #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) 58 59 /******************************************************************************* 60 * Infra IOMMU related constants 61 ******************************************************************************/ 62 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 63 #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00002000) 64 #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 65 #define PERICFG_AO_REG_SIZE (0x1000) 66 67 /******************************************************************************* 68 * GIC-600 & interrupt handling related constants 69 ******************************************************************************/ 70 /* Base MTK_platform compatible GIC memory map */ 71 #define BASE_GICD_BASE (MT_GIC_BASE) 72 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 73 74 /******************************************************************************* 75 * CIRQ related constants 76 ******************************************************************************/ 77 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 78 #define MD_WDT_IRQ_BIT_ID (141) 79 #define CIRQ_IRQ_NUM (730) 80 #define CIRQ_REG_NUM (23) 81 #define CIRQ_SPI_START (96) 82 83 /******************************************************************************* 84 * MM IOMMU & SMI related constants 85 ******************************************************************************/ 86 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 87 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 88 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 89 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 90 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 91 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 92 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 93 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 94 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 95 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 96 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 97 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 98 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 99 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 100 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 101 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 102 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 103 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 104 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 105 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 106 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 107 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 108 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 109 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 110 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 111 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 112 #define SMI_LARB_REG_RNG_SIZE (0x1000) 113 114 /******************************************************************************* 115 * SPM related constants 116 ******************************************************************************/ 117 #define SPM_BASE (IO_PHYS + 0x00006000) 118 119 /******************************************************************************* 120 * APMIXEDSYS related constants 121 ******************************************************************************/ 122 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 123 124 /******************************************************************************* 125 * VPPSYS related constants 126 ******************************************************************************/ 127 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 128 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 129 130 /******************************************************************************* 131 * VDOSYS related constants 132 ******************************************************************************/ 133 #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 134 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 135 136 /******************************************************************************* 137 * SSPM_MBOX_3 related constants 138 ******************************************************************************/ 139 #define SSPM_MBOX_3_BASE (IO_PHYS + 0x00480000) 140 141 /******************************************************************************* 142 * DP related constants 143 ******************************************************************************/ 144 #define EDP_SEC_BASE (IO_PHYS + 0x0C504000) 145 #define DP_SEC_BASE (IO_PHYS + 0x0C604000) 146 #define EDP_SEC_SIZE (0x1000) 147 #define DP_SEC_SIZE (0x1000) 148 149 /******************************************************************************* 150 * EMI MPU related constants 151 *******************************************************************************/ 152 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) 153 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000) 154 155 /******************************************************************************* 156 * System counter frequency related constants 157 ******************************************************************************/ 158 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 159 #define SYS_COUNTER_FREQ_IN_MHZ (13) 160 161 /******************************************************************************* 162 * Platform binary types for linking 163 ******************************************************************************/ 164 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 165 #define PLATFORM_LINKER_ARCH aarch64 166 167 /******************************************************************************* 168 * Generic platform constants 169 ******************************************************************************/ 170 #define PLATFORM_STACK_SIZE (0x800) 171 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 172 #define SOC_CHIP_ID U(0x8188) 173 174 /******************************************************************************* 175 * Platform memory map related constants 176 ******************************************************************************/ 177 #define TZRAM_BASE (0x54600000) 178 #define TZRAM_SIZE (0x00030000) 179 180 /******************************************************************************* 181 * BL31 specific defines. 182 ******************************************************************************/ 183 /* 184 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 185 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 186 * little space for growth. 187 */ 188 #define BL31_BASE (TZRAM_BASE + 0x1000) 189 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 190 191 /******************************************************************************* 192 * Platform specific page table and MMU setup constants 193 ******************************************************************************/ 194 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 195 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 196 #define MAX_XLAT_TABLES (16) 197 #define MAX_MMAP_REGIONS (16) 198 199 /******************************************************************************* 200 * CPU_EB TCM handling related constants 201 ******************************************************************************/ 202 #define CPU_EB_TCM_BASE (0x0C550000) 203 #define CPU_EB_TCM_SIZE (0x10000) 204 #define CPU_EB_MBOX3_OFFSET (0xFCE0) 205 206 /******************************************************************************* 207 * CPU PM definitions 208 *******************************************************************************/ 209 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 210 #define PLAT_CPU_PM_ILDO_ID (6) 211 #define CPU_IDLE_SRAM_BASE (0x11B000) 212 #define CPU_IDLE_SRAM_SIZE (0x1000) 213 214 #endif /* PLATFORM_DEF_H */ 215