1*27132f13SRex-BC Chen# 2*27132f13SRex-BC Chen# Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*27132f13SRex-BC Chen# 4*27132f13SRex-BC Chen# SPDX-License-Identifier: BSD-3-Clause 5*27132f13SRex-BC Chen# 6*27132f13SRex-BC Chen 7*27132f13SRex-BC ChenMTK_PLAT := plat/mediatek 8*27132f13SRex-BC ChenMTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} 9*27132f13SRex-BC Chen 10*27132f13SRex-BC ChenPLAT_INCLUDES := -I${MTK_PLAT}/common/ \ 11*27132f13SRex-BC Chen -I${MTK_PLAT_SOC}/include/ 12*27132f13SRex-BC Chen 13*27132f13SRex-BC Cheninclude drivers/arm/gic/v3/gicv3.mk 14*27132f13SRex-BC Cheninclude lib/xlat_tables_v2/xlat_tables.mk 15*27132f13SRex-BC Chen 16*27132f13SRex-BC ChenPLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \ 17*27132f13SRex-BC Chen ${XLAT_TABLES_LIB_SRCS} \ 18*27132f13SRex-BC Chen plat/common/aarch64/crash_console_helpers.S \ 19*27132f13SRex-BC Chen plat/common/plat_psci_common.c 20*27132f13SRex-BC Chen 21*27132f13SRex-BC Chen 22*27132f13SRex-BC ChenBL31_SOURCES += common/desc_image_load.c \ 23*27132f13SRex-BC Chen drivers/ti/uart/aarch64/16550_console.S \ 24*27132f13SRex-BC Chen lib/bl_aux_params/bl_aux_params.c \ 25*27132f13SRex-BC Chen lib/cpus/aarch64/cortex_a55.S \ 26*27132f13SRex-BC Chen lib/cpus/aarch64/cortex_a76.S \ 27*27132f13SRex-BC Chen plat/common/plat_gicv3.c \ 28*27132f13SRex-BC Chen ${MTK_PLAT}/common/mtk_plat_common.c \ 29*27132f13SRex-BC Chen ${MTK_PLAT}/common/params_setup.c \ 30*27132f13SRex-BC Chen ${MTK_PLAT_SOC}/aarch64/platform_common.c \ 31*27132f13SRex-BC Chen ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ 32*27132f13SRex-BC Chen ${MTK_PLAT_SOC}/bl31_plat_setup.c \ 33*27132f13SRex-BC Chen ${MTK_PLAT_SOC}/plat_pm.c \ 34*27132f13SRex-BC Chen ${MTK_PLAT_SOC}/plat_topology.c 35*27132f13SRex-BC Chen 36*27132f13SRex-BC Chen# Configs for A76 and A55 37*27132f13SRex-BC ChenHW_ASSISTED_COHERENCY := 1 38*27132f13SRex-BC ChenUSE_COHERENT_MEM := 0 39*27132f13SRex-BC ChenCTX_INCLUDE_AARCH32_REGS := 0 40*27132f13SRex-BC ChenERRATA_A55_1530923 := 1 41*27132f13SRex-BC ChenERRATA_A55_1221012 := 1 42*27132f13SRex-BC Chen 43*27132f13SRex-BC Chen# indicate the reset vector address can be programmed 44*27132f13SRex-BC ChenPROGRAMMABLE_RESET_ADDRESS := 1 45*27132f13SRex-BC Chen 46*27132f13SRex-BC ChenCOLD_BOOT_SINGLE_CPU := 1 47*27132f13SRex-BC Chen 48*27132f13SRex-BC ChenMACH_MT8186 := 1 49*27132f13SRex-BC Chen$(eval $(call add_define,MACH_MT8186)) 50*27132f13SRex-BC Chen 51*27132f13SRex-BC Cheninclude lib/coreboot/coreboot.mk 52