1*7ac6a76cSjason-ch chen /* 2*7ac6a76cSjason-ch chen * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*7ac6a76cSjason-ch chen * 4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause 5*7ac6a76cSjason-ch chen */ 6*7ac6a76cSjason-ch chen 7*7ac6a76cSjason-ch chen #ifndef __SSPM_REG_H__ 8*7ac6a76cSjason-ch chen #define __SSPM_REG_H__ 9*7ac6a76cSjason-ch chen 10*7ac6a76cSjason-ch chen #include "platform_def.h" 11*7ac6a76cSjason-ch chen 12*7ac6a76cSjason-ch chen #define SSPM_CFGREG_BASE (IO_PHYS + 0x440000) /* SSPM view: 0x30040000 */ 13*7ac6a76cSjason-ch chen #define SSPM_CFGREG_ADDR(ofs) (SSPM_CFGREG_BASE + (ofs)) 14*7ac6a76cSjason-ch chen 15*7ac6a76cSjason-ch chen #define SSPM_MCDI_SHARE_SRAM (IO_PHYS + 0x420000) 16*7ac6a76cSjason-ch chen #define SSPM_MBOX_3_BASE (IO_PHYS + 0x480000) 17*7ac6a76cSjason-ch chen 18*7ac6a76cSjason-ch chen #define SSPM_HW_SEM SSPM_CFGREG_ADDR(0x0048) 19*7ac6a76cSjason-ch chen #define SSPM_ACAO_INT_SET SSPM_CFGREG_ADDR(0x00D8) 20*7ac6a76cSjason-ch chen #define SSPM_ACAO_INT_CLR SSPM_CFGREG_ADDR(0x00DC) 21*7ac6a76cSjason-ch chen 22*7ac6a76cSjason-ch chen #define STANDBYWFI_EN(n) (1 << (n + 8)) 23*7ac6a76cSjason-ch chen #define GIC_IRQOUT_EN(n) (1 << (n + 0)) 24*7ac6a76cSjason-ch chen 25*7ac6a76cSjason-ch chen #endif /* __SSPM_REG_H__ */ 26