1*7ac6a76cSjason-ch chen /* 2*7ac6a76cSjason-ch chen * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*7ac6a76cSjason-ch chen * 4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause 5*7ac6a76cSjason-ch chen */ 6*7ac6a76cSjason-ch chen 7*7ac6a76cSjason-ch chen #ifndef __PLAT_UART_H__ 8*7ac6a76cSjason-ch chen #define __PLAT_UART_H__ 9*7ac6a76cSjason-ch chen 10*7ac6a76cSjason-ch chen /* UART error code */ 11*7ac6a76cSjason-ch chen #define UART_DONE U(0) 12*7ac6a76cSjason-ch chen #define UART_PM_ERROR U(1) 13*7ac6a76cSjason-ch chen 14*7ac6a76cSjason-ch chen /* UART HW information */ 15*7ac6a76cSjason-ch chen #ifndef HW_SUPPORT_UART_PORTS 16*7ac6a76cSjason-ch chen #define HW_SUPPORT_UART_PORTS (2U) /* the UART PORTs current HW have */ 17*7ac6a76cSjason-ch chen #endif 18*7ac6a76cSjason-ch chen #define MTK_UART_SEND_SLEEP_REQ (1U) /* Request uart to sleep */ 19*7ac6a76cSjason-ch chen #define MTK_UART_SLEEP_ACK_IDLE (1U) /* uart in idle state */ 20*7ac6a76cSjason-ch chen #define MTK_UART_WAIT_ACK_TIMES (50U) 21*7ac6a76cSjason-ch chen 22*7ac6a76cSjason-ch chen #define UART_BASE0 (0x11002000) 23*7ac6a76cSjason-ch chen #define UART_BASE1 (0x11003000) 24*7ac6a76cSjason-ch chen 25*7ac6a76cSjason-ch chen #endif /* __PLAT_UART_H__ */ 26