1*1da57e54SGarmin.Chang /* 2*1da57e54SGarmin.Chang * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*1da57e54SGarmin.Chang * 4*1da57e54SGarmin.Chang * SPDX-License-Identifier: BSD-3-Clause 5*1da57e54SGarmin.Chang */ 6*1da57e54SGarmin.Chang 7*1da57e54SGarmin.Chang #ifndef PLAT_PM_H 8*1da57e54SGarmin.Chang #define PLAT_PM_H 9*1da57e54SGarmin.Chang 10*1da57e54SGarmin.Chang #include <lib/utils_def.h> 11*1da57e54SGarmin.Chang 12*1da57e54SGarmin.Chang #define MT_PLAT_PWR_STATE_CPU U(1) 13*1da57e54SGarmin.Chang #define MT_PLAT_PWR_STATE_CLUSTER U(2) 14*1da57e54SGarmin.Chang #define MT_PLAT_PWR_STATE_MCUSYS U(3) 15*1da57e54SGarmin.Chang #define MT_PLAT_PWR_STATE_SUSPEND2IDLE U(8) 16*1da57e54SGarmin.Chang #define MT_PLAT_PWR_STATE_SYSTEM_SUSPEND U(9) 17*1da57e54SGarmin.Chang 18*1da57e54SGarmin.Chang #define MTK_LOCAL_STATE_RUN U(0) 19*1da57e54SGarmin.Chang #define MTK_LOCAL_STATE_RET U(1) 20*1da57e54SGarmin.Chang #define MTK_LOCAL_STATE_OFF U(2) 21*1da57e54SGarmin.Chang 22*1da57e54SGarmin.Chang #define MTK_AFFLVL_CPU U(0) 23*1da57e54SGarmin.Chang #define MTK_AFFLVL_CLUSTER U(1) 24*1da57e54SGarmin.Chang #define MTK_AFFLVL_MCUSYS U(2) 25*1da57e54SGarmin.Chang #define MTK_AFFLVL_SYSTEM U(3) 26*1da57e54SGarmin.Chang 27*1da57e54SGarmin.Chang #define IS_CLUSTER_OFF_STATE(s) \ 28*1da57e54SGarmin.Chang is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER]) 29*1da57e54SGarmin.Chang #define IS_MCUSYS_OFF_STATE(s) \ 30*1da57e54SGarmin.Chang is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS]) 31*1da57e54SGarmin.Chang #define IS_SYSTEM_SUSPEND_STATE(s) \ 32*1da57e54SGarmin.Chang is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM]) 33*1da57e54SGarmin.Chang 34*1da57e54SGarmin.Chang #define IS_PLAT_SUSPEND_ID(stateid) \ 35*1da57e54SGarmin.Chang ((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE) \ 36*1da57e54SGarmin.Chang || (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND)) 37*1da57e54SGarmin.Chang 38*1da57e54SGarmin.Chang #endif /* PLAT_PM_H */ 39