1*1da57e54SGarmin.Chang /* 2*1da57e54SGarmin.Chang * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*1da57e54SGarmin.Chang * 4*1da57e54SGarmin.Chang * SPDX-License-Identifier: BSD-3-Clause 5*1da57e54SGarmin.Chang */ 6*1da57e54SGarmin.Chang 7*1da57e54SGarmin.Chang #ifndef PLAT_MTK_LPM_H 8*1da57e54SGarmin.Chang #define PLAT_MTK_LPM_H 9*1da57e54SGarmin.Chang 10*1da57e54SGarmin.Chang #include <lib/psci/psci.h> 11*1da57e54SGarmin.Chang #include <lib/utils_def.h> 12*1da57e54SGarmin.Chang 13*1da57e54SGarmin.Chang #define MT_IRQ_REMAIN_MAX U(32) 14*1da57e54SGarmin.Chang #define MT_IRQ_REMAIN_CAT_LOG BIT(31) 15*1da57e54SGarmin.Chang 16*1da57e54SGarmin.Chang struct mt_irqremain { 17*1da57e54SGarmin.Chang unsigned int count; 18*1da57e54SGarmin.Chang unsigned int irqs[MT_IRQ_REMAIN_MAX]; 19*1da57e54SGarmin.Chang unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX]; 20*1da57e54SGarmin.Chang unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX]; 21*1da57e54SGarmin.Chang }; 22*1da57e54SGarmin.Chang 23*1da57e54SGarmin.Chang #define PLAT_RC_STATUS_READY BIT(0) 24*1da57e54SGarmin.Chang #define PLAT_RC_STATUS_FEATURE_EN BIT(1) 25*1da57e54SGarmin.Chang #define PLAT_RC_STATUS_UART_NONSLEEP BIT(31) 26*1da57e54SGarmin.Chang 27*1da57e54SGarmin.Chang struct mt_lpm_tz { 28*1da57e54SGarmin.Chang int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state); 29*1da57e54SGarmin.Chang int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state); 30*1da57e54SGarmin.Chang 31*1da57e54SGarmin.Chang int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state); 32*1da57e54SGarmin.Chang int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state); 33*1da57e54SGarmin.Chang 34*1da57e54SGarmin.Chang int (*pwr_cluster_on)(unsigned int cpu, 35*1da57e54SGarmin.Chang const psci_power_state_t *state); 36*1da57e54SGarmin.Chang int (*pwr_cluster_dwn)(unsigned int cpu, 37*1da57e54SGarmin.Chang const psci_power_state_t *state); 38*1da57e54SGarmin.Chang 39*1da57e54SGarmin.Chang int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state); 40*1da57e54SGarmin.Chang int (*pwr_mcusys_on_finished)(unsigned int cpu, 41*1da57e54SGarmin.Chang const psci_power_state_t *state); 42*1da57e54SGarmin.Chang int (*pwr_mcusys_dwn)(unsigned int cpu, 43*1da57e54SGarmin.Chang const psci_power_state_t *state); 44*1da57e54SGarmin.Chang }; 45*1da57e54SGarmin.Chang 46*1da57e54SGarmin.Chang const struct mt_lpm_tz *mt_plat_cpu_pm_init(void); 47*1da57e54SGarmin.Chang 48*1da57e54SGarmin.Chang #endif /* PLAT_MTK_LPM_H */ 49