1*7ac6a76cSjason-ch chen /* 2*7ac6a76cSjason-ch chen * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*7ac6a76cSjason-ch chen * 4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause 5*7ac6a76cSjason-ch chen */ 6*7ac6a76cSjason-ch chen 7*7ac6a76cSjason-ch chen #ifndef MT_SPM_RESOURCE_REQ_H 8*7ac6a76cSjason-ch chen #define MT_SPM_RESOURCE_REQ_H 9*7ac6a76cSjason-ch chen 10*7ac6a76cSjason-ch chen /* SPM resource request internal bit */ 11*7ac6a76cSjason-ch chen #define MT_SPM_BIT_XO_FPM (0U) 12*7ac6a76cSjason-ch chen #define MT_SPM_BIT_26M (1U) 13*7ac6a76cSjason-ch chen #define MT_SPM_BIT_INFRA (2U) 14*7ac6a76cSjason-ch chen #define MT_SPM_BIT_SYSPLL (3U) 15*7ac6a76cSjason-ch chen #define MT_SPM_BIT_DRAM_S0 (4U) 16*7ac6a76cSjason-ch chen #define MT_SPM_BIT_DRAM_S1 (5U) 17*7ac6a76cSjason-ch chen 18*7ac6a76cSjason-ch chen /* SPM resource request internal bit_mask */ 19*7ac6a76cSjason-ch chen #define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM) 20*7ac6a76cSjason-ch chen #define MT_SPM_26M BIT(MT_SPM_BIT_26M) 21*7ac6a76cSjason-ch chen #define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA) 22*7ac6a76cSjason-ch chen #define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL) 23*7ac6a76cSjason-ch chen #define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0) 24*7ac6a76cSjason-ch chen #define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1) 25*7ac6a76cSjason-ch chen 26*7ac6a76cSjason-ch chen char spm_resource_req(unsigned int user, unsigned int req_mask); 27*7ac6a76cSjason-ch chen 28*7ac6a76cSjason-ch chen #define IS_PLAT_SUSPEND_ID(stateid)\ 29*7ac6a76cSjason-ch chen ((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)\ 30*7ac6a76cSjason-ch chen || (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND)) 31*7ac6a76cSjason-ch chen 32*7ac6a76cSjason-ch chen #endif /* MT_SPM_RESOURCE_REQ_H */ 33