xref: /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.h (revision 1f4adc3a34f80249d40bfc7033a65f4217d7ee04)
1*7ac6a76cSjason-ch chen /*
2*7ac6a76cSjason-ch chen  * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3*7ac6a76cSjason-ch chen  *
4*7ac6a76cSjason-ch chen  * SPDX-License-Identifier: BSD-3-Clause
5*7ac6a76cSjason-ch chen  */
6*7ac6a76cSjason-ch chen 
7*7ac6a76cSjason-ch chen 
8*7ac6a76cSjason-ch chen #ifndef MT_SPM_SUSPEDN_H
9*7ac6a76cSjason-ch chen #define MT_SPM_SUSPEDN_H
10*7ac6a76cSjason-ch chen 
11*7ac6a76cSjason-ch chen #include <mt_spm_internal.h>
12*7ac6a76cSjason-ch chen 
13*7ac6a76cSjason-ch chen #define MCUPM_MBOX_OFFSET_PDN	(0x0C55FDA8)
14*7ac6a76cSjason-ch chen #define MCUPM_POWER_DOWN	(0x4D50444E)
15*7ac6a76cSjason-ch chen 
16*7ac6a76cSjason-ch chen enum MT_SPM_SUSPEND_MODE {
17*7ac6a76cSjason-ch chen 	MT_SPM_SUSPEND_SYSTEM_PDN	= 0U,
18*7ac6a76cSjason-ch chen 	MT_SPM_SUSPEND_SLEEP		= 1U,
19*7ac6a76cSjason-ch chen };
20*7ac6a76cSjason-ch chen 
21*7ac6a76cSjason-ch chen extern int mt_spm_suspend_mode_set(int mode);
22*7ac6a76cSjason-ch chen extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
23*7ac6a76cSjason-ch chen 				unsigned int reosuce_req);
24*7ac6a76cSjason-ch chen extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
25*7ac6a76cSjason-ch chen 				  struct wake_status **status);
26*7ac6a76cSjason-ch chen extern void mt_spm_suspend_init(void);
27*7ac6a76cSjason-ch chen 
28*7ac6a76cSjason-ch chen #endif /* MT_SPM_SUSPEND_H */
29