1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <lib/mmio.h> 9 #include <mt_spm.h> 10 #include <mt_spm_conservation.h> 11 #include <mt_spm_internal.h> 12 #include <mt_spm_rc_internal.h> 13 #include <mt_spm_reg.h> 14 #include <mt_spm_resource_req.h> 15 #include <mt_spm_suspend.h> 16 #include <plat_pm.h> 17 #include <uart.h> 18 19 #define SPM_SUSPEND_SLEEP_PCM_FLAG \ 20 (SPM_FLAG_DISABLE_INFRA_PDN | \ 21 SPM_FLAG_DISABLE_VCORE_DVS | \ 22 SPM_FLAG_DISABLE_VCORE_DFS | \ 23 SPM_FLAG_USE_SRCCLKENO2) 24 25 #define SPM_SUSPEND_SLEEP_PCM_FLAG1 (0U) 26 27 #define SPM_SUSPEND_PCM_FLAG \ 28 (SPM_FLAG_DISABLE_VCORE_DVS | \ 29 SPM_FLAG_DISABLE_VCORE_DFS) 30 31 #define SPM_SUSPEND_PCM_FLAG1 (0U) 32 33 #define __WAKE_SRC_FOR_SUSPEND_COMMON__ \ 34 (R12_PCM_TIMER | \ 35 R12_KP_IRQ_B | \ 36 R12_APWDT_EVENT_B | \ 37 R12_CONN2AP_SPM_WAKEUP_B | \ 38 R12_EINT_EVENT_B | \ 39 R12_CONN_WDT_IRQ_B | \ 40 R12_SSPM2SPM_WAKEUP_B | \ 41 R12_SCP2SPM_WAKEUP_B | \ 42 R12_ADSP2SPM_WAKEUP_B | \ 43 R12_USBX_CDSC_B | \ 44 R12_USBX_POWERDWN_B | \ 45 R12_SYS_TIMER_EVENT_B | \ 46 R12_EINT_EVENT_SECURE_B | \ 47 R12_SYS_CIRQ_IRQ_B | \ 48 R12_NNA_WAKEUP | \ 49 R12_REG_CPU_WAKEUP) 50 51 #if defined(CFG_MICROTRUST_TEE_SUPPORT) 52 #define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__) 53 #else 54 #define WAKE_SRC_FOR_SUSPEND \ 55 (__WAKE_SRC_FOR_SUSPEND_COMMON__ | \ 56 R12_SEJ_EVENT_B) 57 #endif 58 59 static struct pwr_ctrl suspend_ctrl = { 60 .wake_src = WAKE_SRC_FOR_SUSPEND, 61 62 /* Auto-gen Start */ 63 64 /* SPM_AP_STANDBY_CON */ 65 .reg_wfi_op = 0, 66 .reg_wfi_type = 0, 67 .reg_mp0_cputop_idle_mask = 0, 68 .reg_mp1_cputop_idle_mask = 0, 69 .reg_mcusys_idle_mask = 0, 70 .reg_md_apsrc_1_sel = 0, 71 .reg_md_apsrc_0_sel = 0, 72 .reg_conn_apsrc_sel = 0, 73 74 /* SPM_SRC6_MASK */ 75 .reg_ccif_event_infra_req_mask_b = 0, 76 .reg_ccif_event_apsrc_req_mask_b = 0, 77 78 /* SPM_SRC_REQ */ 79 .reg_spm_apsrc_req = 0, 80 .reg_spm_f26m_req = 0, 81 .reg_spm_infra_req = 0, 82 .reg_spm_vrf18_req = 0, 83 .reg_spm_ddren_req = 0, 84 .reg_spm_dvfs_req = 0, 85 .reg_spm_sw_mailbox_req = 0, 86 .reg_spm_sspm_mailbox_req = 0, 87 .reg_spm_adsp_mailbox_req = 0, 88 .reg_spm_scp_mailbox_req = 0, 89 90 /* SPM_SRC_MASK */ 91 .reg_md_0_srcclkena_mask_b = 0, 92 .reg_md_0_infra_req_mask_b = 0, 93 .reg_md_0_apsrc_req_mask_b = 0, 94 .reg_md_0_vrf18_req_mask_b = 0, 95 .reg_md_0_ddren_req_mask_b = 0, 96 .reg_md_1_srcclkena_mask_b = 0, 97 .reg_md_1_infra_req_mask_b = 0, 98 .reg_md_1_apsrc_req_mask_b = 0, 99 .reg_md_1_vrf18_req_mask_b = 0, 100 .reg_md_1_ddren_req_mask_b = 0, 101 .reg_conn_srcclkena_mask_b = 1, 102 .reg_conn_srcclkenb_mask_b = 0, 103 .reg_conn_infra_req_mask_b = 1, 104 .reg_conn_apsrc_req_mask_b = 1, 105 .reg_conn_vrf18_req_mask_b = 1, 106 .reg_conn_ddren_req_mask_b = 1, 107 .reg_conn_vfe28_mask_b = 0, 108 .reg_srcclkeni_srcclkena_mask_b = 1, 109 .reg_srcclkeni_infra_req_mask_b = 1, 110 .reg_infrasys_apsrc_req_mask_b = 0, 111 .reg_infrasys_ddren_req_mask_b = 1, 112 .reg_sspm_srcclkena_mask_b = 1, 113 .reg_sspm_infra_req_mask_b = 1, 114 .reg_sspm_apsrc_req_mask_b = 1, 115 .reg_sspm_vrf18_req_mask_b = 1, 116 .reg_sspm_ddren_req_mask_b = 1, 117 118 /* SPM_SRC2_MASK */ 119 .reg_scp_srcclkena_mask_b = 1, 120 .reg_scp_infra_req_mask_b = 1, 121 .reg_scp_apsrc_req_mask_b = 1, 122 .reg_scp_vrf18_req_mask_b = 1, 123 .reg_scp_ddren_req_mask_b = 1, 124 .reg_audio_dsp_srcclkena_mask_b = 1, 125 .reg_audio_dsp_infra_req_mask_b = 1, 126 .reg_audio_dsp_apsrc_req_mask_b = 1, 127 .reg_audio_dsp_vrf18_req_mask_b = 1, 128 .reg_audio_dsp_ddren_req_mask_b = 1, 129 .reg_ufs_srcclkena_mask_b = 1, 130 .reg_ufs_infra_req_mask_b = 1, 131 .reg_ufs_apsrc_req_mask_b = 1, 132 .reg_ufs_vrf18_req_mask_b = 1, 133 .reg_ufs_ddren_req_mask_b = 1, 134 .reg_disp0_apsrc_req_mask_b = 1, 135 .reg_disp0_ddren_req_mask_b = 1, 136 .reg_disp1_apsrc_req_mask_b = 1, 137 .reg_disp1_ddren_req_mask_b = 1, 138 .reg_gce_infra_req_mask_b = 1, 139 .reg_gce_apsrc_req_mask_b = 1, 140 .reg_gce_vrf18_req_mask_b = 1, 141 .reg_gce_ddren_req_mask_b = 1, 142 .reg_apu_srcclkena_mask_b = 0, 143 .reg_apu_infra_req_mask_b = 0, 144 .reg_apu_apsrc_req_mask_b = 0, 145 .reg_apu_vrf18_req_mask_b = 0, 146 .reg_apu_ddren_req_mask_b = 0, 147 .reg_cg_check_srcclkena_mask_b = 0, 148 .reg_cg_check_apsrc_req_mask_b = 0, 149 .reg_cg_check_vrf18_req_mask_b = 0, 150 .reg_cg_check_ddren_req_mask_b = 0, 151 152 /* SPM_SRC3_MASK */ 153 .reg_dvfsrc_event_trigger_mask_b = 1, 154 .reg_sw2spm_wakeup_mask_b = 0, 155 .reg_adsp2spm_wakeup_mask_b = 0, 156 .reg_sspm2spm_wakeup_mask_b = 0, 157 .reg_scp2spm_wakeup_mask_b = 0, 158 .reg_csyspwrup_ack_mask = 1, 159 .reg_spm_reserved_srcclkena_mask_b = 0, 160 .reg_spm_reserved_infra_req_mask_b = 0, 161 .reg_spm_reserved_apsrc_req_mask_b = 0, 162 .reg_spm_reserved_vrf18_req_mask_b = 0, 163 .reg_spm_reserved_ddren_req_mask_b = 0, 164 .reg_mcupm_srcclkena_mask_b = 0, 165 .reg_mcupm_infra_req_mask_b = 0, 166 .reg_mcupm_apsrc_req_mask_b = 0, 167 .reg_mcupm_vrf18_req_mask_b = 0, 168 .reg_mcupm_ddren_req_mask_b = 0, 169 .reg_msdc0_srcclkena_mask_b = 1, 170 .reg_msdc0_infra_req_mask_b = 1, 171 .reg_msdc0_apsrc_req_mask_b = 1, 172 .reg_msdc0_vrf18_req_mask_b = 1, 173 .reg_msdc0_ddren_req_mask_b = 1, 174 .reg_msdc1_srcclkena_mask_b = 1, 175 .reg_msdc1_infra_req_mask_b = 1, 176 .reg_msdc1_apsrc_req_mask_b = 1, 177 .reg_msdc1_vrf18_req_mask_b = 1, 178 .reg_msdc1_ddren_req_mask_b = 1, 179 180 /* SPM_SRC4_MASK */ 181 .reg_ccif_event_srcclkena_mask_b = 0, 182 .reg_bak_psri_srcclkena_mask_b = 0, 183 .reg_bak_psri_infra_req_mask_b = 0, 184 .reg_bak_psri_apsrc_req_mask_b = 0, 185 .reg_bak_psri_vrf18_req_mask_b = 0, 186 .reg_bak_psri_ddren_req_mask_b = 0, 187 .reg_dramc_md32_infra_req_mask_b = 0, 188 .reg_dramc_md32_vrf18_req_mask_b = 0, 189 .reg_conn_srcclkenb2pwrap_mask_b = 0, 190 .reg_dramc_md32_apsrc_req_mask_b = 0, 191 192 /* SPM_SRC5_MASK */ 193 .reg_mcusys_merge_apsrc_req_mask_b = 0x83, 194 .reg_mcusys_merge_ddren_req_mask_b = 0x83, 195 .reg_afe_srcclkena_mask_b = 1, 196 .reg_afe_infra_req_mask_b = 1, 197 .reg_afe_apsrc_req_mask_b = 1, 198 .reg_afe_vrf18_req_mask_b = 1, 199 .reg_afe_ddren_req_mask_b = 1, 200 .reg_msdc2_srcclkena_mask_b = 0, 201 .reg_msdc2_infra_req_mask_b = 0, 202 .reg_msdc2_apsrc_req_mask_b = 0, 203 .reg_msdc2_vrf18_req_mask_b = 0, 204 .reg_msdc2_ddren_req_mask_b = 0, 205 206 /* SPM_WAKEUP_EVENT_MASK */ 207 .reg_wakeup_event_mask = 0x1383213, 208 209 /* SPM_WAKEUP_EVENT_EXT_MASK */ 210 .reg_ext_wakeup_event_mask = 0xFFFFFFFF, 211 212 /* SPM_SRC7_MASK */ 213 .reg_pcie_srcclkena_mask_b = 0, 214 .reg_pcie_infra_req_mask_b = 0, 215 .reg_pcie_apsrc_req_mask_b = 0, 216 .reg_pcie_vrf18_req_mask_b = 0, 217 .reg_pcie_ddren_req_mask_b = 0, 218 .reg_dpmaif_srcclkena_mask_b = 1, 219 .reg_dpmaif_infra_req_mask_b = 1, 220 .reg_dpmaif_apsrc_req_mask_b = 1, 221 .reg_dpmaif_vrf18_req_mask_b = 1, 222 .reg_dpmaif_ddren_req_mask_b = 1, 223 224 /* Auto-gen End */ 225 226 /*sw flag setting */ 227 .pcm_flags = SPM_SUSPEND_PCM_FLAG, 228 .pcm_flags1 = SPM_SUSPEND_PCM_FLAG1, 229 }; 230 231 struct spm_lp_scen __spm_suspend = { 232 .pwrctrl = &suspend_ctrl, 233 }; 234 235 int mt_spm_suspend_mode_set(int mode) 236 { 237 if (mode == MT_SPM_SUSPEND_SLEEP) { 238 suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG; 239 suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1; 240 } else { 241 suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG; 242 suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1; 243 } 244 245 return 0; 246 } 247 248 int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, 249 unsigned int resource_req) 250 { 251 /* If FMAudio / ADSP is active, change to sleep suspend mode */ 252 if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) { 253 mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP); 254 } 255 256 /* Notify MCUPM that device is going suspend flow */ 257 mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN); 258 259 /* Notify UART to sleep */ 260 mt_uart_save(); 261 262 return spm_conservation(state_id, ext_opand, 263 &__spm_suspend, resource_req); 264 } 265 266 void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, 267 struct wake_status **status) 268 { 269 spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status); 270 271 /* Notify UART to wakeup */ 272 mt_uart_restore(); 273 274 /* Notify MCUPM that device leave suspend */ 275 mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0); 276 277 /* If FMAudio / ADSP is active, change back to suspend mode */ 278 if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) { 279 mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN); 280 } 281 } 282 283 void mt_spm_suspend_init(void) 284 { 285 spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl); 286 } 287