1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <lib/mmio.h> 9 #include <mt_spm.h> 10 #include <mt_spm_conservation.h> 11 #include <mt_spm_idle.h> 12 #include <mt_spm_internal.h> 13 #include <mt_spm_reg.h> 14 #include <mt_spm_resource_req.h> 15 #include <plat_pm.h> 16 17 #define __WAKE_SRC_FOR_SUSPEND_COMMON__ \ 18 (R12_PCM_TIMER | \ 19 R12_KP_IRQ_B | \ 20 R12_APWDT_EVENT_B | \ 21 R12_APXGPT1_EVENT_B | \ 22 R12_CONN2AP_SPM_WAKEUP_B | \ 23 R12_EINT_EVENT_B | \ 24 R12_CONN_WDT_IRQ_B | \ 25 R12_SSPM2SPM_WAKEUP_B | \ 26 R12_SCP2SPM_WAKEUP_B | \ 27 R12_ADSP2SPM_WAKEUP_B | \ 28 R12_USBX_CDSC_B | \ 29 R12_USBX_POWERDWN_B | \ 30 R12_SYS_TIMER_EVENT_B | \ 31 R12_EINT_EVENT_SECURE_B | \ 32 R12_AFE_IRQ_MCU_B | \ 33 R12_SYS_CIRQ_IRQ_B | \ 34 R12_NNA_WAKEUP | \ 35 R12_SEJ_EVENT_B | \ 36 R12_REG_CPU_WAKEUP) 37 38 #if defined(CFG_MICROTRUST_TEE_SUPPORT) 39 #define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__) 40 #else 41 #define WAKE_SRC_FOR_SUSPEND \ 42 (__WAKE_SRC_FOR_SUSPEND_COMMON__ | \ 43 R12_SEJ_EVENT_B) 44 #endif 45 46 static struct pwr_ctrl idle_spm_pwr = { 47 .timer_val = 0x28000, 48 .wake_src = WAKE_SRC_FOR_SUSPEND, 49 /* Auto-gen Start */ 50 51 /* SPM_AP_STANDBY_CON */ 52 .reg_wfi_op = 0, 53 .reg_wfi_type = 0, 54 .reg_mp0_cputop_idle_mask = 0, 55 .reg_mp1_cputop_idle_mask = 0, 56 .reg_mcusys_idle_mask = 0, 57 .reg_md_apsrc_1_sel = 0, 58 .reg_md_apsrc_0_sel = 0, 59 .reg_conn_apsrc_sel = 0, 60 61 /* SPM_SRC6_MASK */ 62 .reg_ccif_event_infra_req_mask_b = 0, 63 .reg_ccif_event_apsrc_req_mask_b = 0, 64 65 /* SPM_SRC_REQ */ 66 .reg_spm_apsrc_req = 0, 67 .reg_spm_f26m_req = 0, 68 .reg_spm_infra_req = 0, 69 .reg_spm_vrf18_req = 0, 70 .reg_spm_ddren_req = 0, 71 .reg_spm_dvfs_req = 0, 72 .reg_spm_sw_mailbox_req = 0, 73 .reg_spm_sspm_mailbox_req = 0, 74 .reg_spm_adsp_mailbox_req = 0, 75 .reg_spm_scp_mailbox_req = 0, 76 77 /* SPM_SRC_MASK */ 78 .reg_md_0_srcclkena_mask_b = 0, 79 .reg_md_0_infra_req_mask_b = 0, 80 .reg_md_0_apsrc_req_mask_b = 0, 81 .reg_md_0_vrf18_req_mask_b = 0, 82 .reg_md_0_ddren_req_mask_b = 0, 83 .reg_md_1_srcclkena_mask_b = 0, 84 .reg_md_1_infra_req_mask_b = 0, 85 .reg_md_1_apsrc_req_mask_b = 0, 86 .reg_md_1_vrf18_req_mask_b = 0, 87 .reg_md_1_ddren_req_mask_b = 0, 88 .reg_conn_srcclkena_mask_b = 1, 89 .reg_conn_srcclkenb_mask_b = 0, 90 .reg_conn_infra_req_mask_b = 1, 91 .reg_conn_apsrc_req_mask_b = 1, 92 .reg_conn_vrf18_req_mask_b = 1, 93 .reg_conn_ddren_req_mask_b = 1, 94 .reg_conn_vfe28_mask_b = 0, 95 .reg_srcclkeni_srcclkena_mask_b = 1, 96 .reg_srcclkeni_infra_req_mask_b = 1, 97 .reg_infrasys_apsrc_req_mask_b = 0, 98 .reg_infrasys_ddren_req_mask_b = 1, 99 .reg_sspm_srcclkena_mask_b = 1, 100 .reg_sspm_infra_req_mask_b = 1, 101 .reg_sspm_apsrc_req_mask_b = 1, 102 .reg_sspm_vrf18_req_mask_b = 1, 103 .reg_sspm_ddren_req_mask_b = 1, 104 105 /* SPM_SRC2_MASK */ 106 .reg_scp_srcclkena_mask_b = 1, 107 .reg_scp_infra_req_mask_b = 1, 108 .reg_scp_apsrc_req_mask_b = 1, 109 .reg_scp_vrf18_req_mask_b = 1, 110 .reg_scp_ddren_req_mask_b = 1, 111 .reg_audio_dsp_srcclkena_mask_b = 1, 112 .reg_audio_dsp_infra_req_mask_b = 1, 113 .reg_audio_dsp_apsrc_req_mask_b = 1, 114 .reg_audio_dsp_vrf18_req_mask_b = 1, 115 .reg_audio_dsp_ddren_req_mask_b = 1, 116 .reg_ufs_srcclkena_mask_b = 1, 117 .reg_ufs_infra_req_mask_b = 1, 118 .reg_ufs_apsrc_req_mask_b = 1, 119 .reg_ufs_vrf18_req_mask_b = 1, 120 .reg_ufs_ddren_req_mask_b = 1, 121 .reg_disp0_apsrc_req_mask_b = 1, 122 .reg_disp0_ddren_req_mask_b = 1, 123 .reg_disp1_apsrc_req_mask_b = 1, 124 .reg_disp1_ddren_req_mask_b = 1, 125 .reg_gce_infra_req_mask_b = 1, 126 .reg_gce_apsrc_req_mask_b = 1, 127 .reg_gce_vrf18_req_mask_b = 1, 128 .reg_gce_ddren_req_mask_b = 1, 129 .reg_apu_srcclkena_mask_b = 0, 130 .reg_apu_infra_req_mask_b = 0, 131 .reg_apu_apsrc_req_mask_b = 0, 132 .reg_apu_vrf18_req_mask_b = 0, 133 .reg_apu_ddren_req_mask_b = 0, 134 .reg_cg_check_srcclkena_mask_b = 0, 135 .reg_cg_check_apsrc_req_mask_b = 0, 136 .reg_cg_check_vrf18_req_mask_b = 0, 137 .reg_cg_check_ddren_req_mask_b = 0, 138 139 /* SPM_SRC3_MASK */ 140 .reg_dvfsrc_event_trigger_mask_b = 1, 141 .reg_sw2spm_wakeup_mask_b = 0, 142 .reg_adsp2spm_wakeup_mask_b = 0, 143 .reg_sspm2spm_wakeup_mask_b = 0, 144 .reg_scp2spm_wakeup_mask_b = 0, 145 .reg_csyspwrup_ack_mask = 1, 146 .reg_spm_reserved_srcclkena_mask_b = 0, 147 .reg_spm_reserved_infra_req_mask_b = 0, 148 .reg_spm_reserved_apsrc_req_mask_b = 0, 149 .reg_spm_reserved_vrf18_req_mask_b = 0, 150 .reg_spm_reserved_ddren_req_mask_b = 0, 151 .reg_mcupm_srcclkena_mask_b = 0, 152 .reg_mcupm_infra_req_mask_b = 0, 153 .reg_mcupm_apsrc_req_mask_b = 0, 154 .reg_mcupm_vrf18_req_mask_b = 0, 155 .reg_mcupm_ddren_req_mask_b = 0, 156 .reg_msdc0_srcclkena_mask_b = 1, 157 .reg_msdc0_infra_req_mask_b = 1, 158 .reg_msdc0_apsrc_req_mask_b = 1, 159 .reg_msdc0_vrf18_req_mask_b = 1, 160 .reg_msdc0_ddren_req_mask_b = 1, 161 .reg_msdc1_srcclkena_mask_b = 1, 162 .reg_msdc1_infra_req_mask_b = 1, 163 .reg_msdc1_apsrc_req_mask_b = 1, 164 .reg_msdc1_vrf18_req_mask_b = 1, 165 .reg_msdc1_ddren_req_mask_b = 1, 166 167 /* SPM_SRC4_MASK */ 168 .reg_ccif_event_srcclkena_mask_b = 0, 169 .reg_bak_psri_srcclkena_mask_b = 0, 170 .reg_bak_psri_infra_req_mask_b = 0, 171 .reg_bak_psri_apsrc_req_mask_b = 0, 172 .reg_bak_psri_vrf18_req_mask_b = 0, 173 .reg_bak_psri_ddren_req_mask_b = 0, 174 .reg_dramc_md32_infra_req_mask_b = 0, 175 .reg_dramc_md32_vrf18_req_mask_b = 0, 176 .reg_conn_srcclkenb2pwrap_mask_b = 0, 177 .reg_dramc_md32_apsrc_req_mask_b = 0, 178 179 /* SPM_SRC5_MASK */ 180 .reg_mcusys_merge_apsrc_req_mask_b = 0x83, 181 .reg_mcusys_merge_ddren_req_mask_b = 0x83, 182 .reg_afe_srcclkena_mask_b = 1, 183 .reg_afe_infra_req_mask_b = 1, 184 .reg_afe_apsrc_req_mask_b = 1, 185 .reg_afe_vrf18_req_mask_b = 1, 186 .reg_afe_ddren_req_mask_b = 1, 187 .reg_msdc2_srcclkena_mask_b = 0, 188 .reg_msdc2_infra_req_mask_b = 0, 189 .reg_msdc2_apsrc_req_mask_b = 0, 190 .reg_msdc2_vrf18_req_mask_b = 0, 191 .reg_msdc2_ddren_req_mask_b = 0, 192 193 /* SPM_WAKEUP_EVENT_MASK */ 194 .reg_wakeup_event_mask = 0xE1283203, 195 196 /* SPM_WAKEUP_EVENT_EXT_MASK */ 197 .reg_ext_wakeup_event_mask = 0xFFFFFFFF, 198 199 /* SPM_SRC7_MASK */ 200 .reg_pcie_srcclkena_mask_b = 0, 201 .reg_pcie_infra_req_mask_b = 0, 202 .reg_pcie_apsrc_req_mask_b = 0, 203 .reg_pcie_vrf18_req_mask_b = 0, 204 .reg_pcie_ddren_req_mask_b = 0, 205 .reg_dpmaif_srcclkena_mask_b = 1, 206 .reg_dpmaif_infra_req_mask_b = 1, 207 .reg_dpmaif_apsrc_req_mask_b = 1, 208 .reg_dpmaif_vrf18_req_mask_b = 1, 209 .reg_dpmaif_ddren_req_mask_b = 1, 210 211 /* Auto-gen End */ 212 }; 213 214 struct spm_lp_scen idle_spm_lp = { 215 .pwrctrl = &idle_spm_pwr, 216 }; 217 218 int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, 219 spm_idle_conduct fn) 220 { 221 unsigned int src_req = 0U; 222 223 if (fn != NULL) { 224 fn(&idle_spm_lp, &src_req); 225 } 226 227 return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req); 228 } 229 void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand, 230 struct wake_status **status, 231 spm_idle_conduct_restore fn) 232 { 233 ext_opand |= (MT_SPM_EX_OP_TIME_CHECK | MT_SPM_EX_OP_TIME_OBS); 234 spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status); 235 } 236 237 void mt_spm_idle_generic_init(void) 238 { 239 spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl); 240 } 241