1*7ac6a76cSjason-ch chen /*
2*7ac6a76cSjason-ch chen * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3*7ac6a76cSjason-ch chen *
4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause
5*7ac6a76cSjason-ch chen */
6*7ac6a76cSjason-ch chen
7*7ac6a76cSjason-ch chen #include <common/debug.h>
8*7ac6a76cSjason-ch chen #include <lib/mmio.h>
9*7ac6a76cSjason-ch chen #include <mt_spm.h>
10*7ac6a76cSjason-ch chen #include <mt_spm_conservation.h>
11*7ac6a76cSjason-ch chen #include <mt_spm_idle.h>
12*7ac6a76cSjason-ch chen #include <mt_spm_internal.h>
13*7ac6a76cSjason-ch chen #include <mt_spm_reg.h>
14*7ac6a76cSjason-ch chen #include <mt_spm_resource_req.h>
15*7ac6a76cSjason-ch chen #include <plat_pm.h>
16*7ac6a76cSjason-ch chen
17*7ac6a76cSjason-ch chen #define __WAKE_SRC_FOR_SUSPEND_COMMON__ \
18*7ac6a76cSjason-ch chen (R12_PCM_TIMER | \
19*7ac6a76cSjason-ch chen R12_KP_IRQ_B | \
20*7ac6a76cSjason-ch chen R12_APWDT_EVENT_B | \
21*7ac6a76cSjason-ch chen R12_APXGPT1_EVENT_B | \
22*7ac6a76cSjason-ch chen R12_CONN2AP_SPM_WAKEUP_B | \
23*7ac6a76cSjason-ch chen R12_EINT_EVENT_B | \
24*7ac6a76cSjason-ch chen R12_CONN_WDT_IRQ_B | \
25*7ac6a76cSjason-ch chen R12_SSPM2SPM_WAKEUP_B | \
26*7ac6a76cSjason-ch chen R12_SCP2SPM_WAKEUP_B | \
27*7ac6a76cSjason-ch chen R12_ADSP2SPM_WAKEUP_B | \
28*7ac6a76cSjason-ch chen R12_USBX_CDSC_B | \
29*7ac6a76cSjason-ch chen R12_USBX_POWERDWN_B | \
30*7ac6a76cSjason-ch chen R12_SYS_TIMER_EVENT_B | \
31*7ac6a76cSjason-ch chen R12_EINT_EVENT_SECURE_B | \
32*7ac6a76cSjason-ch chen R12_AFE_IRQ_MCU_B | \
33*7ac6a76cSjason-ch chen R12_SYS_CIRQ_IRQ_B | \
34*7ac6a76cSjason-ch chen R12_NNA_WAKEUP | \
35*7ac6a76cSjason-ch chen R12_SEJ_EVENT_B | \
36*7ac6a76cSjason-ch chen R12_REG_CPU_WAKEUP)
37*7ac6a76cSjason-ch chen
38*7ac6a76cSjason-ch chen #if defined(CFG_MICROTRUST_TEE_SUPPORT)
39*7ac6a76cSjason-ch chen #define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
40*7ac6a76cSjason-ch chen #else
41*7ac6a76cSjason-ch chen #define WAKE_SRC_FOR_SUSPEND \
42*7ac6a76cSjason-ch chen (__WAKE_SRC_FOR_SUSPEND_COMMON__ | \
43*7ac6a76cSjason-ch chen R12_SEJ_EVENT_B)
44*7ac6a76cSjason-ch chen #endif
45*7ac6a76cSjason-ch chen
46*7ac6a76cSjason-ch chen static struct pwr_ctrl idle_spm_pwr = {
47*7ac6a76cSjason-ch chen .timer_val = 0x28000,
48*7ac6a76cSjason-ch chen .wake_src = WAKE_SRC_FOR_SUSPEND,
49*7ac6a76cSjason-ch chen /* Auto-gen Start */
50*7ac6a76cSjason-ch chen
51*7ac6a76cSjason-ch chen /* SPM_AP_STANDBY_CON */
52*7ac6a76cSjason-ch chen .reg_wfi_op = 0,
53*7ac6a76cSjason-ch chen .reg_wfi_type = 0,
54*7ac6a76cSjason-ch chen .reg_mp0_cputop_idle_mask = 0,
55*7ac6a76cSjason-ch chen .reg_mp1_cputop_idle_mask = 0,
56*7ac6a76cSjason-ch chen .reg_mcusys_idle_mask = 0,
57*7ac6a76cSjason-ch chen .reg_md_apsrc_1_sel = 0,
58*7ac6a76cSjason-ch chen .reg_md_apsrc_0_sel = 0,
59*7ac6a76cSjason-ch chen .reg_conn_apsrc_sel = 0,
60*7ac6a76cSjason-ch chen
61*7ac6a76cSjason-ch chen /* SPM_SRC6_MASK */
62*7ac6a76cSjason-ch chen .reg_ccif_event_infra_req_mask_b = 0,
63*7ac6a76cSjason-ch chen .reg_ccif_event_apsrc_req_mask_b = 0,
64*7ac6a76cSjason-ch chen
65*7ac6a76cSjason-ch chen /* SPM_SRC_REQ */
66*7ac6a76cSjason-ch chen .reg_spm_apsrc_req = 0,
67*7ac6a76cSjason-ch chen .reg_spm_f26m_req = 0,
68*7ac6a76cSjason-ch chen .reg_spm_infra_req = 0,
69*7ac6a76cSjason-ch chen .reg_spm_vrf18_req = 0,
70*7ac6a76cSjason-ch chen .reg_spm_ddren_req = 0,
71*7ac6a76cSjason-ch chen .reg_spm_dvfs_req = 0,
72*7ac6a76cSjason-ch chen .reg_spm_sw_mailbox_req = 0,
73*7ac6a76cSjason-ch chen .reg_spm_sspm_mailbox_req = 0,
74*7ac6a76cSjason-ch chen .reg_spm_adsp_mailbox_req = 0,
75*7ac6a76cSjason-ch chen .reg_spm_scp_mailbox_req = 0,
76*7ac6a76cSjason-ch chen
77*7ac6a76cSjason-ch chen /* SPM_SRC_MASK */
78*7ac6a76cSjason-ch chen .reg_md_0_srcclkena_mask_b = 0,
79*7ac6a76cSjason-ch chen .reg_md_0_infra_req_mask_b = 0,
80*7ac6a76cSjason-ch chen .reg_md_0_apsrc_req_mask_b = 0,
81*7ac6a76cSjason-ch chen .reg_md_0_vrf18_req_mask_b = 0,
82*7ac6a76cSjason-ch chen .reg_md_0_ddren_req_mask_b = 0,
83*7ac6a76cSjason-ch chen .reg_md_1_srcclkena_mask_b = 0,
84*7ac6a76cSjason-ch chen .reg_md_1_infra_req_mask_b = 0,
85*7ac6a76cSjason-ch chen .reg_md_1_apsrc_req_mask_b = 0,
86*7ac6a76cSjason-ch chen .reg_md_1_vrf18_req_mask_b = 0,
87*7ac6a76cSjason-ch chen .reg_md_1_ddren_req_mask_b = 0,
88*7ac6a76cSjason-ch chen .reg_conn_srcclkena_mask_b = 1,
89*7ac6a76cSjason-ch chen .reg_conn_srcclkenb_mask_b = 0,
90*7ac6a76cSjason-ch chen .reg_conn_infra_req_mask_b = 1,
91*7ac6a76cSjason-ch chen .reg_conn_apsrc_req_mask_b = 1,
92*7ac6a76cSjason-ch chen .reg_conn_vrf18_req_mask_b = 1,
93*7ac6a76cSjason-ch chen .reg_conn_ddren_req_mask_b = 1,
94*7ac6a76cSjason-ch chen .reg_conn_vfe28_mask_b = 0,
95*7ac6a76cSjason-ch chen .reg_srcclkeni_srcclkena_mask_b = 1,
96*7ac6a76cSjason-ch chen .reg_srcclkeni_infra_req_mask_b = 1,
97*7ac6a76cSjason-ch chen .reg_infrasys_apsrc_req_mask_b = 0,
98*7ac6a76cSjason-ch chen .reg_infrasys_ddren_req_mask_b = 1,
99*7ac6a76cSjason-ch chen .reg_sspm_srcclkena_mask_b = 1,
100*7ac6a76cSjason-ch chen .reg_sspm_infra_req_mask_b = 1,
101*7ac6a76cSjason-ch chen .reg_sspm_apsrc_req_mask_b = 1,
102*7ac6a76cSjason-ch chen .reg_sspm_vrf18_req_mask_b = 1,
103*7ac6a76cSjason-ch chen .reg_sspm_ddren_req_mask_b = 1,
104*7ac6a76cSjason-ch chen
105*7ac6a76cSjason-ch chen /* SPM_SRC2_MASK */
106*7ac6a76cSjason-ch chen .reg_scp_srcclkena_mask_b = 1,
107*7ac6a76cSjason-ch chen .reg_scp_infra_req_mask_b = 1,
108*7ac6a76cSjason-ch chen .reg_scp_apsrc_req_mask_b = 1,
109*7ac6a76cSjason-ch chen .reg_scp_vrf18_req_mask_b = 1,
110*7ac6a76cSjason-ch chen .reg_scp_ddren_req_mask_b = 1,
111*7ac6a76cSjason-ch chen .reg_audio_dsp_srcclkena_mask_b = 1,
112*7ac6a76cSjason-ch chen .reg_audio_dsp_infra_req_mask_b = 1,
113*7ac6a76cSjason-ch chen .reg_audio_dsp_apsrc_req_mask_b = 1,
114*7ac6a76cSjason-ch chen .reg_audio_dsp_vrf18_req_mask_b = 1,
115*7ac6a76cSjason-ch chen .reg_audio_dsp_ddren_req_mask_b = 1,
116*7ac6a76cSjason-ch chen .reg_ufs_srcclkena_mask_b = 1,
117*7ac6a76cSjason-ch chen .reg_ufs_infra_req_mask_b = 1,
118*7ac6a76cSjason-ch chen .reg_ufs_apsrc_req_mask_b = 1,
119*7ac6a76cSjason-ch chen .reg_ufs_vrf18_req_mask_b = 1,
120*7ac6a76cSjason-ch chen .reg_ufs_ddren_req_mask_b = 1,
121*7ac6a76cSjason-ch chen .reg_disp0_apsrc_req_mask_b = 1,
122*7ac6a76cSjason-ch chen .reg_disp0_ddren_req_mask_b = 1,
123*7ac6a76cSjason-ch chen .reg_disp1_apsrc_req_mask_b = 1,
124*7ac6a76cSjason-ch chen .reg_disp1_ddren_req_mask_b = 1,
125*7ac6a76cSjason-ch chen .reg_gce_infra_req_mask_b = 1,
126*7ac6a76cSjason-ch chen .reg_gce_apsrc_req_mask_b = 1,
127*7ac6a76cSjason-ch chen .reg_gce_vrf18_req_mask_b = 1,
128*7ac6a76cSjason-ch chen .reg_gce_ddren_req_mask_b = 1,
129*7ac6a76cSjason-ch chen .reg_apu_srcclkena_mask_b = 0,
130*7ac6a76cSjason-ch chen .reg_apu_infra_req_mask_b = 0,
131*7ac6a76cSjason-ch chen .reg_apu_apsrc_req_mask_b = 0,
132*7ac6a76cSjason-ch chen .reg_apu_vrf18_req_mask_b = 0,
133*7ac6a76cSjason-ch chen .reg_apu_ddren_req_mask_b = 0,
134*7ac6a76cSjason-ch chen .reg_cg_check_srcclkena_mask_b = 0,
135*7ac6a76cSjason-ch chen .reg_cg_check_apsrc_req_mask_b = 0,
136*7ac6a76cSjason-ch chen .reg_cg_check_vrf18_req_mask_b = 0,
137*7ac6a76cSjason-ch chen .reg_cg_check_ddren_req_mask_b = 0,
138*7ac6a76cSjason-ch chen
139*7ac6a76cSjason-ch chen /* SPM_SRC3_MASK */
140*7ac6a76cSjason-ch chen .reg_dvfsrc_event_trigger_mask_b = 1,
141*7ac6a76cSjason-ch chen .reg_sw2spm_wakeup_mask_b = 0,
142*7ac6a76cSjason-ch chen .reg_adsp2spm_wakeup_mask_b = 0,
143*7ac6a76cSjason-ch chen .reg_sspm2spm_wakeup_mask_b = 0,
144*7ac6a76cSjason-ch chen .reg_scp2spm_wakeup_mask_b = 0,
145*7ac6a76cSjason-ch chen .reg_csyspwrup_ack_mask = 1,
146*7ac6a76cSjason-ch chen .reg_spm_reserved_srcclkena_mask_b = 0,
147*7ac6a76cSjason-ch chen .reg_spm_reserved_infra_req_mask_b = 0,
148*7ac6a76cSjason-ch chen .reg_spm_reserved_apsrc_req_mask_b = 0,
149*7ac6a76cSjason-ch chen .reg_spm_reserved_vrf18_req_mask_b = 0,
150*7ac6a76cSjason-ch chen .reg_spm_reserved_ddren_req_mask_b = 0,
151*7ac6a76cSjason-ch chen .reg_mcupm_srcclkena_mask_b = 0,
152*7ac6a76cSjason-ch chen .reg_mcupm_infra_req_mask_b = 0,
153*7ac6a76cSjason-ch chen .reg_mcupm_apsrc_req_mask_b = 0,
154*7ac6a76cSjason-ch chen .reg_mcupm_vrf18_req_mask_b = 0,
155*7ac6a76cSjason-ch chen .reg_mcupm_ddren_req_mask_b = 0,
156*7ac6a76cSjason-ch chen .reg_msdc0_srcclkena_mask_b = 1,
157*7ac6a76cSjason-ch chen .reg_msdc0_infra_req_mask_b = 1,
158*7ac6a76cSjason-ch chen .reg_msdc0_apsrc_req_mask_b = 1,
159*7ac6a76cSjason-ch chen .reg_msdc0_vrf18_req_mask_b = 1,
160*7ac6a76cSjason-ch chen .reg_msdc0_ddren_req_mask_b = 1,
161*7ac6a76cSjason-ch chen .reg_msdc1_srcclkena_mask_b = 1,
162*7ac6a76cSjason-ch chen .reg_msdc1_infra_req_mask_b = 1,
163*7ac6a76cSjason-ch chen .reg_msdc1_apsrc_req_mask_b = 1,
164*7ac6a76cSjason-ch chen .reg_msdc1_vrf18_req_mask_b = 1,
165*7ac6a76cSjason-ch chen .reg_msdc1_ddren_req_mask_b = 1,
166*7ac6a76cSjason-ch chen
167*7ac6a76cSjason-ch chen /* SPM_SRC4_MASK */
168*7ac6a76cSjason-ch chen .reg_ccif_event_srcclkena_mask_b = 0,
169*7ac6a76cSjason-ch chen .reg_bak_psri_srcclkena_mask_b = 0,
170*7ac6a76cSjason-ch chen .reg_bak_psri_infra_req_mask_b = 0,
171*7ac6a76cSjason-ch chen .reg_bak_psri_apsrc_req_mask_b = 0,
172*7ac6a76cSjason-ch chen .reg_bak_psri_vrf18_req_mask_b = 0,
173*7ac6a76cSjason-ch chen .reg_bak_psri_ddren_req_mask_b = 0,
174*7ac6a76cSjason-ch chen .reg_dramc_md32_infra_req_mask_b = 0,
175*7ac6a76cSjason-ch chen .reg_dramc_md32_vrf18_req_mask_b = 0,
176*7ac6a76cSjason-ch chen .reg_conn_srcclkenb2pwrap_mask_b = 0,
177*7ac6a76cSjason-ch chen .reg_dramc_md32_apsrc_req_mask_b = 0,
178*7ac6a76cSjason-ch chen
179*7ac6a76cSjason-ch chen /* SPM_SRC5_MASK */
180*7ac6a76cSjason-ch chen .reg_mcusys_merge_apsrc_req_mask_b = 0x83,
181*7ac6a76cSjason-ch chen .reg_mcusys_merge_ddren_req_mask_b = 0x83,
182*7ac6a76cSjason-ch chen .reg_afe_srcclkena_mask_b = 1,
183*7ac6a76cSjason-ch chen .reg_afe_infra_req_mask_b = 1,
184*7ac6a76cSjason-ch chen .reg_afe_apsrc_req_mask_b = 1,
185*7ac6a76cSjason-ch chen .reg_afe_vrf18_req_mask_b = 1,
186*7ac6a76cSjason-ch chen .reg_afe_ddren_req_mask_b = 1,
187*7ac6a76cSjason-ch chen .reg_msdc2_srcclkena_mask_b = 0,
188*7ac6a76cSjason-ch chen .reg_msdc2_infra_req_mask_b = 0,
189*7ac6a76cSjason-ch chen .reg_msdc2_apsrc_req_mask_b = 0,
190*7ac6a76cSjason-ch chen .reg_msdc2_vrf18_req_mask_b = 0,
191*7ac6a76cSjason-ch chen .reg_msdc2_ddren_req_mask_b = 0,
192*7ac6a76cSjason-ch chen
193*7ac6a76cSjason-ch chen /* SPM_WAKEUP_EVENT_MASK */
194*7ac6a76cSjason-ch chen .reg_wakeup_event_mask = 0xE1283203,
195*7ac6a76cSjason-ch chen
196*7ac6a76cSjason-ch chen /* SPM_WAKEUP_EVENT_EXT_MASK */
197*7ac6a76cSjason-ch chen .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
198*7ac6a76cSjason-ch chen
199*7ac6a76cSjason-ch chen /* SPM_SRC7_MASK */
200*7ac6a76cSjason-ch chen .reg_pcie_srcclkena_mask_b = 0,
201*7ac6a76cSjason-ch chen .reg_pcie_infra_req_mask_b = 0,
202*7ac6a76cSjason-ch chen .reg_pcie_apsrc_req_mask_b = 0,
203*7ac6a76cSjason-ch chen .reg_pcie_vrf18_req_mask_b = 0,
204*7ac6a76cSjason-ch chen .reg_pcie_ddren_req_mask_b = 0,
205*7ac6a76cSjason-ch chen .reg_dpmaif_srcclkena_mask_b = 1,
206*7ac6a76cSjason-ch chen .reg_dpmaif_infra_req_mask_b = 1,
207*7ac6a76cSjason-ch chen .reg_dpmaif_apsrc_req_mask_b = 1,
208*7ac6a76cSjason-ch chen .reg_dpmaif_vrf18_req_mask_b = 1,
209*7ac6a76cSjason-ch chen .reg_dpmaif_ddren_req_mask_b = 1,
210*7ac6a76cSjason-ch chen
211*7ac6a76cSjason-ch chen /* Auto-gen End */
212*7ac6a76cSjason-ch chen };
213*7ac6a76cSjason-ch chen
214*7ac6a76cSjason-ch chen struct spm_lp_scen idle_spm_lp = {
215*7ac6a76cSjason-ch chen .pwrctrl = &idle_spm_pwr,
216*7ac6a76cSjason-ch chen };
217*7ac6a76cSjason-ch chen
mt_spm_idle_generic_enter(int state_id,unsigned int ext_opand,spm_idle_conduct fn)218*7ac6a76cSjason-ch chen int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
219*7ac6a76cSjason-ch chen spm_idle_conduct fn)
220*7ac6a76cSjason-ch chen {
221*7ac6a76cSjason-ch chen unsigned int src_req = 0U;
222*7ac6a76cSjason-ch chen
223*7ac6a76cSjason-ch chen if (fn != NULL) {
224*7ac6a76cSjason-ch chen fn(&idle_spm_lp, &src_req);
225*7ac6a76cSjason-ch chen }
226*7ac6a76cSjason-ch chen
227*7ac6a76cSjason-ch chen return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
228*7ac6a76cSjason-ch chen }
mt_spm_idle_generic_resume(int state_id,unsigned int ext_opand,struct wake_status ** status,spm_idle_conduct_restore fn)229*7ac6a76cSjason-ch chen void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
230*7ac6a76cSjason-ch chen struct wake_status **status,
231*7ac6a76cSjason-ch chen spm_idle_conduct_restore fn)
232*7ac6a76cSjason-ch chen {
233*7ac6a76cSjason-ch chen ext_opand |= (MT_SPM_EX_OP_TIME_CHECK | MT_SPM_EX_OP_TIME_OBS);
234*7ac6a76cSjason-ch chen spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
235*7ac6a76cSjason-ch chen }
236*7ac6a76cSjason-ch chen
mt_spm_idle_generic_init(void)237*7ac6a76cSjason-ch chen void mt_spm_idle_generic_init(void)
238*7ac6a76cSjason-ch chen {
239*7ac6a76cSjason-ch chen spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
240*7ac6a76cSjason-ch chen }
241