1*7ac6a76cSjason-ch chen /* 2*7ac6a76cSjason-ch chen * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*7ac6a76cSjason-ch chen * 4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause 5*7ac6a76cSjason-ch chen */ 6*7ac6a76cSjason-ch chen 7*7ac6a76cSjason-ch chen #ifndef MT_SPM_CONSTRAINT_H 8*7ac6a76cSjason-ch chen #define MT_SPM_CONSTRAINT_H 9*7ac6a76cSjason-ch chen 10*7ac6a76cSjason-ch chen #include <mt_lp_rm.h> 11*7ac6a76cSjason-ch chen 12*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF BIT(0) 13*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 BIT(1) 14*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 BIT(2) 15*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_VCORE_LP BIT(3) 16*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN BIT(4) 17*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF BIT(5) 18*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND BIT(6) 19*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_BBLPM BIT(7) 20*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_XO_UFS BIT(8) 21*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_GPS_STATE BIT(9) 22*7ac6a76cSjason-ch chen #define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE BIT(10) 23*7ac6a76cSjason-ch chen 24*7ac6a76cSjason-ch chen #define MT_SPM_RC_INVALID (0x0) 25*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID_SW BIT(0) 26*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID_FW BIT(1) 27*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID_RESIDNECY BIT(2) 28*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID_COND_CHECK BIT(3) 29*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID_COND_LATCH BIT(4) 30*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID_UFS_H8 BIT(5) 31*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID_FLIGHTMODE BIT(6) 32*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID_XSOC_BBLPM BIT(7) 33*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID_TRACE_EVENT BIT(8) 34*7ac6a76cSjason-ch chen 35*7ac6a76cSjason-ch chen #define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW) 36*7ac6a76cSjason-ch chen 37*7ac6a76cSjason-ch chen #define IS_MT_RM_RC_READY(status) \ 38*7ac6a76cSjason-ch chen ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID) 39*7ac6a76cSjason-ch chen 40*7ac6a76cSjason-ch chen #define MT_SPM_RC_BBLPM_MODE \ 41*7ac6a76cSjason-ch chen (MT_SPM_RC_VALID_UFS_H8 | \ 42*7ac6a76cSjason-ch chen MT_SPM_RC_VALID_FLIGHTMODE | \ 43*7ac6a76cSjason-ch chen MT_SPM_RC_VALID_XSOC_BBLPM) 44*7ac6a76cSjason-ch chen 45*7ac6a76cSjason-ch chen #define IS_MT_SPM_RC_BBLPM_MODE(st) \ 46*7ac6a76cSjason-ch chen ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE) 47*7ac6a76cSjason-ch chen 48*7ac6a76cSjason-ch chen struct constraint_status { 49*7ac6a76cSjason-ch chen uint16_t id; 50*7ac6a76cSjason-ch chen uint16_t valid; 51*7ac6a76cSjason-ch chen uint32_t cond_block; 52*7ac6a76cSjason-ch chen uint32_t enter_cnt; 53*7ac6a76cSjason-ch chen struct mt_spm_cond_tables *cond_res; 54*7ac6a76cSjason-ch chen }; 55*7ac6a76cSjason-ch chen 56*7ac6a76cSjason-ch chen enum MT_SPM_RM_RC_TYPE { 57*7ac6a76cSjason-ch chen MT_RM_CONSTRAINT_ID_BUS26M = 0U, 58*7ac6a76cSjason-ch chen MT_RM_CONSTRAINT_ID_SYSPLL = 1U, 59*7ac6a76cSjason-ch chen MT_RM_CONSTRAINT_ID_DRAM = 2U, 60*7ac6a76cSjason-ch chen MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO = 3U, 61*7ac6a76cSjason-ch chen MT_RM_CONSTRAINT_ID_ALL = 4U, 62*7ac6a76cSjason-ch chen }; 63*7ac6a76cSjason-ch chen 64*7ac6a76cSjason-ch chen #endif /* MT_SPM_CONSTRAINT_H */ 65