1*7ac6a76cSjason-ch chen /*
2*7ac6a76cSjason-ch chen * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3*7ac6a76cSjason-ch chen *
4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause
5*7ac6a76cSjason-ch chen */
6*7ac6a76cSjason-ch chen
7*7ac6a76cSjason-ch chen #ifndef MT_SPM_H
8*7ac6a76cSjason-ch chen #define MT_SPM_H
9*7ac6a76cSjason-ch chen
10*7ac6a76cSjason-ch chen #include <lib/bakery_lock.h>
11*7ac6a76cSjason-ch chen #include <lib/spinlock.h>
12*7ac6a76cSjason-ch chen #include <plat_mtk_lpm.h>
13*7ac6a76cSjason-ch chen
14*7ac6a76cSjason-ch chen /*
15*7ac6a76cSjason-ch chen * ARM v8.2, the cache will turn off automatically when cpu
16*7ac6a76cSjason-ch chen * power down. Therefore, there is no doubt to use the spin_lock here.
17*7ac6a76cSjason-ch chen */
18*7ac6a76cSjason-ch chen #if !HW_ASSISTED_COHERENCY
19*7ac6a76cSjason-ch chen #define MT_SPM_USING_BAKERY_LOCK
20*7ac6a76cSjason-ch chen #endif
21*7ac6a76cSjason-ch chen
22*7ac6a76cSjason-ch chen #ifdef MT_SPM_USING_BAKERY_LOCK
23*7ac6a76cSjason-ch chen DECLARE_BAKERY_LOCK(spm_lock);
24*7ac6a76cSjason-ch chen #define plat_spm_lock() bakery_lock_get(&spm_lock)
25*7ac6a76cSjason-ch chen #define plat_spm_unlock() bakery_lock_release(&spm_lock)
26*7ac6a76cSjason-ch chen #else
27*7ac6a76cSjason-ch chen extern spinlock_t spm_lock;
28*7ac6a76cSjason-ch chen #define plat_spm_lock() spin_lock(&spm_lock)
29*7ac6a76cSjason-ch chen #define plat_spm_unlock() spin_unlock(&spm_lock)
30*7ac6a76cSjason-ch chen #endif
31*7ac6a76cSjason-ch chen
32*7ac6a76cSjason-ch chen #define MT_SPM_USING_SRCLKEN_RC
33*7ac6a76cSjason-ch chen
34*7ac6a76cSjason-ch chen /* spm extern operand definition */
35*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_CLR_26M_RECORD BIT(0)
36*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_SET_WDT BIT(1)
37*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ BIT(2)
38*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_SET_SUSPEND_MODE BIT(3)
39*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_SET_IS_ADSP BIT(4)
40*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM BIT(5)
41*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_HW_S1_DETECT BIT(6)
42*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_TRACE_LP BIT(7)
43*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_TRACE_SUSPEND BIT(8)
44*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_TRACE_TIMESTAMP_EN BIT(9)
45*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_TIME_CHECK BIT(10)
46*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_TIME_OBS BIT(11)
47*7ac6a76cSjason-ch chen
48*7ac6a76cSjason-ch chen typedef enum {
49*7ac6a76cSjason-ch chen WR_NONE = 0,
50*7ac6a76cSjason-ch chen WR_UART_BUSY = 1,
51*7ac6a76cSjason-ch chen WR_ABORT = 2,
52*7ac6a76cSjason-ch chen WR_PCM_TIMER = 3,
53*7ac6a76cSjason-ch chen WR_WAKE_SRC = 4,
54*7ac6a76cSjason-ch chen WR_DVFSRC = 5,
55*7ac6a76cSjason-ch chen WR_TWAM = 6,
56*7ac6a76cSjason-ch chen WR_PMSR = 7,
57*7ac6a76cSjason-ch chen WR_SPM_ACK_CHK = 8,
58*7ac6a76cSjason-ch chen WR_UNKNOWN = 9,
59*7ac6a76cSjason-ch chen } wake_reason_t;
60*7ac6a76cSjason-ch chen
61*7ac6a76cSjason-ch chen /* for suspend vol. bin settings */
62*7ac6a76cSjason-ch chen enum MT_PLAT_SUSPEND_VCORE {
63*7ac6a76cSjason-ch chen SPM_SUSPEND_VCORE_5500 = 0,
64*7ac6a76cSjason-ch chen SPM_SUSPEND_VCORE_5250 = 1,
65*7ac6a76cSjason-ch chen SPM_SUSPEND_VCORE_5000 = 2,
66*7ac6a76cSjason-ch chen };
67*7ac6a76cSjason-ch chen
68*7ac6a76cSjason-ch chen extern void spm_boot_init(void);
69*7ac6a76cSjason-ch chen
spm_lock_get(void)70*7ac6a76cSjason-ch chen static inline void spm_lock_get(void)
71*7ac6a76cSjason-ch chen {
72*7ac6a76cSjason-ch chen plat_spm_lock();
73*7ac6a76cSjason-ch chen }
74*7ac6a76cSjason-ch chen
spm_lock_release(void)75*7ac6a76cSjason-ch chen static inline void spm_lock_release(void)
76*7ac6a76cSjason-ch chen {
77*7ac6a76cSjason-ch chen plat_spm_unlock();
78*7ac6a76cSjason-ch chen }
79*7ac6a76cSjason-ch chen
80*7ac6a76cSjason-ch chen unsigned int spm_get_suspend_vcore_voltage_idx(void);
81*7ac6a76cSjason-ch chen
82*7ac6a76cSjason-ch chen #endif /* MT_SPM_H */
83